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| cr1901 | I don't have code to share immediately right now, but I found a load-bearing comment that when altered changes yosys' synth_ice40 LUT usage from 860 LUTs to 808 LUTs. Uhhh... | 04:32 |
|---|---|---|
| lofty | cr1901: amazing | 04:36 |
| lofty | which one? :p | 04:36 |
| cr1901 | Not in yosys, in my design (generated from Amaranth). I would expect comments to uhhh... not change the synthesis results that much. | 04:38 |
| cr1901 | Must be a next-gen optimization | 04:38 |
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| cr1901 | Is there a way to change yosys' PRNG seed? Only thing I can think of, unless somehow "attribute enum_values" are special (seems like yosys and Amaranth just emit them, not use them) | 04:52 |
| cr1901 | This is tomorrow me's problem | 04:52 |
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| Myrl-saki | `always @*` vs `assign` doesn't seem to always have the same behavior. | 09:59 |
| Myrl-saki | Heck, `if (p) begin q; r; end` is sometimes different as `if (p) q; if (p) r;` | 09:59 |
| Myrl-saki | What's the reason for this? | 09:59 |
| lofty | What do you mean by "same behaviour"? | 10:00 |
| Myrl-saki | Right, that was a bit vague lol sorry. I mean that it doesn't have the same resource usage. | 10:00 |
| lofty | Well, you do have to consider that Yosys is chaotic; small changes in the source code can have pretty big changes elsewhere | 10:01 |
| lofty | Due to things like hashing and such | 10:01 |
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| Myrl-saki | Ahh thanks. And yeah, I see. So from the PoV of Yosys (as a graph? or RTL?), they're basically the same, but the order that things get applied differ, thus resulting in different resource usage? | 10:03 |
| lofty | Yeah | 10:04 |
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| lofty | A big factor in this is, for example, that Yosys carries source code information around | 10:04 |
| lofty | Like where a cell was defined | 10:04 |
| Myrl-saki | Yeah, I see now. Even changing the order of the assigns change the behavior lol | 10:06 |
| Myrl-saki | Err, not behavior. | 10:06 |
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| Myrl-saki | This is not exactly related, but I feel like I'm getting a very huge "told you so" moment since my shifter is actually the critical path right now. :x | 10:20 |
| Myrl-saki | Now I'm curious how much the order matters! | 10:24 |
| Myrl-saki | Wild, I think changing the order worked. | 10:33 |
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| xiretza[cis] | for some definition of "worked" | 10:41 |
| Myrl-saki | Hm, why does it say the critical path is slower, but the frequnecy can be higher? | 10:57 |
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| lofty | You're going to have to provide more information than that :p | 11:04 |
| Myrl-saki | https://gist.github.com/adrianparvino/9e176cedf748cd88c78863843105521f | 11:07 |
| lofty | it...doesn't say the critical path is slower? | 11:08 |
| lofty | it says it's faster | 11:09 |
| lofty | optimized: Info: 8.6 ns logic, 12.6 ns routing | 11:09 |
| lofty | unoptimized: Info: 9.4 ns logic, 13.4 ns routing | 11:09 |
| Myrl-saki | OH. The calculation is based on posedge -> posedge. What does 'posedge sysclk' -> <async> say? | 11:11 |
| Myrl-saki | Like, what does it erm, mean? | 11:11 |
| lofty | Those refer to timings outside of clock domains, like, to GPIO | 11:11 |
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| Myrl-saki | I might have found something weird. | 22:10 |
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| Myrl-saki | Sigh, what's wrong with Weechat. | 22:10 |
| Myrl-saki | log("meow %d", A.chunks()[0].wire->name.index_); | 22:10 |
| Myrl-saki | sig_alu[RTLIL::SigSig(A, B)].insert(alunode); | 22:10 |
| Myrl-saki | If I load any file before it, I get this. | 22:11 |
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| Myrl-saki | meow 713 creating $alu model for $macc $sub$au.v:20$86. | 22:11 |
| Myrl-saki | meow 712 creating $alu model for $lt$au.v:22$88 ($lt): 2 new $alu | 22:11 |
| Myrl-saki | Despite it being connected to the same wire. | 22:12 |
| Myrl-saki | Ah, there's the yosys_xtrace option | 22:15 |
| Myrl-saki | Ah, found why. It's simpler than that. | 22:17 |
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| Myrl-saki | This line only sometimes runs. if (!subtract_b && B < A && GetSize(B)) { | 22:19 |
| Myrl-saki | So | 22:22 |
| Myrl-saki | I think the point is canonicalization? | 22:22 |
| Myrl-saki | Hm, I don't think I know enough to make judgment. >_< | 22:24 |
| Myrl-saki | What's happening is that this converts `a + b` to `b + a` sometimes, which hinders unification with `a - b`. | 22:25 |
| Myrl-saki | There's the obvious "just remove this canonicalization" but I'm pretty sure that hinders other optimizations. | 22:26 |
| Myrl-saki | (Also, that's not actually the problem, even.) | 22:27 |
| Myrl-saki | Well that's fun. | 22:39 |
| Myrl-saki | I understand the problem now. | 22:39 |
| Myrl-saki | Turns out that cmp also has this canonicalization. | 22:39 |
| Myrl-saki | The problem is then that cmps can swap, but subtracts cannot. | 22:40 |
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| Myrl-saki | Okay, I think I'm happy with this. :) | 22:54 |
| Myrl-saki | Ah. | 23:02 |
| Myrl-saki | I found a failing test. | 23:03 |
| Myrl-saki | Though, I think this is supposedly unobservable behavior. | 23:04 |
| Myrl-saki | FWIW, now that I think about it, I don't have to remove the initial swap. | 23:10 |
| Myrl-saki | Because cmp now just acts as if sig_alu is an order-independent dictionary. | 23:11 |
| Myrl-saki | What's the `GetSize(B)` check there for? | 23:17 |
| Myrl-saki | https://github.com/YosysHQ/yosys/commit/b34ca151853aa2b5052afd56269a53079e17429d | 23:21 |
| Myrl-saki | Ah | 23:21 |
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