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| Myrl-saki | How do I use external, er, libraries? Do I just put it as a Git submodule, and add it to read_Verilog? | 15:34 |
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| lofty | Myrl-saki: they're just files to Yosys | 15:39 |
| Myrl-saki | Yep, just to clarify. I'm asking for what's "usually done" since this is my first project. | 15:39 |
| tnt | Myrl-saki: yeah submodules is a good way imho. | 15:40 |
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| Myrl-saki | I just thought of something and wonder if Yosys implements this. | 18:02 |
| Myrl-saki | https://gist.github.com/adrianparvino/14b2fccec8ab85e525793e6663c922b4 | 18:02 |
| Myrl-saki | Maybe with splitnets? | 18:04 |
| Myrl-saki | o | 18:14 |
| Myrl-saki | Huh. | 19:26 |
| tnt | I mean, it should implementi it just fine but if it's supposed to be a UART RX ... it'll be big ... | 19:34 |
| Myrl-saki | The idea that I had was that this basically works as a demuxer, so the input side doesn't have to be treated anymore. | 19:35 |
| Myrl-saki | While the current implementation seems to be using a mask. (x & mask | y & ~mask) | 19:36 |
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