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| Myrl-saki | How do I make $lsl/$lsr not take 50% of my design? lol | 07:17 |
|---|---|---|
| tnt | Myrl-saki: you need hardware multiplier for that :) | 07:18 |
| tnt | How wide is the datapath ? | 07:18 |
| Myrl-saki | 32-bit, and yes! I'm actually considering figuring out how to get DSP block to work for Gowin lol | 07:19 |
| Myrl-saki | I think it's because Yosys is hyperoptimizing for latency, but I don't think it's even needed. | 07:21 |
| tnt | Shoudl be ... ~224 LUT4s if my math is correct. | 07:22 |
| Myrl-saki | I used to be able to use LUT4 for the shifters only, and use any LUTs everywhere elses. | 07:22 |
| Myrl-saki | But now, even if I techmap to abc it, it gets relutted(?) later. | 07:22 |
| Myrl-saki | I guess I could just not use synth_gowin? | 07:22 |
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| Myrl-saki | Ah whoops | 07:25 |
| Myrl-saki | So I did spam, sorry. | 07:25 |
| Myrl-saki | Meant to send this instead. | 07:25 |
| Myrl-saki | MUX2_LUT5 477 | 07:25 |
| Myrl-saki | MUX2_LUT6 221 | 07:25 |
| Myrl-saki | MUX2_LUT7 69 | 07:25 |
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| Myrl-saki | Huh weird. | 07:25 |
| lofty | [08:21:42] Myrl-saki: I think it's because Yosys is hyperoptimizing for latency, but I don't think it's even needed. <--- actually no, it's really not | 07:25 |
| Myrl-saki | I think Weechat's broken lol | 07:25 |
| lofty | Yosys turns multiplies into shift-and-add, which is generally the fastest way to map them on modern FPGAs without DSPs | 07:27 |
| Myrl-saki | https://github.com/adrianparvino/furv/blob/main/shifter.v | 07:30 |
| Myrl-saki | This is taking 50% of my design | 07:30 |
| Myrl-saki | 25% each shifter, I'm guessing. | 07:30 |
| Myrl-saki | Hmm | 07:30 |
| tnt | Usually you would only use one shifter. And then reverse the bits at the input/output of it. Less costly than 2 full shifters. | 07:31 |
| Myrl-saki | Oh yeah, that's true. | 07:31 |
| lofty | Yeah, one transforms left shifts into right shifts and back again | 07:32 |
| Myrl-saki | Thanks, how about the asr/lsr toggling? | 07:34 |
| lofty | If your shifter takes in the bits to fill, then for ASR it's the sign bit, and for LSR it's zero | 07:35 |
| Myrl-saki | I'm just using `>>` and >>>`. I'm guessing `opt` will just be able to figure out to merge them? | 07:36 |
| lofty | eeeh | 08:06 |
| lofty | I don't know, actually. | 08:06 |
| Myrl-saki | Thanks. :) FIgured something out I think. | 08:12 |
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