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| Myrl-saki | How do I directly use $alu in my code? | 14:19 |
|---|---|---|
| lofty | Myrl-saki: you don't. | 14:23 |
| lofty | Okay, sure, you can instantiate it as \$alu, but saying "I need to instantiate a Yosys cell" outside of Yosys itself is a pretty strong X/Y problem | 14:24 |
| lofty | The job of `alumacc` is to lower things to $alu cells as needed to make them fast | 14:24 |
| Myrl-saki | Yep, that's true. I'm pretty sure this can be unified into a single ALU but I can't seem to make Yosys do it. | 14:25 |
| Myrl-saki | https://github.com/adrianparvino/furv/blob/main/au.v | 14:25 |
| tnt | What's the target fpga ? | 14:25 |
| lofty | Myrl-saki: no, that can't be turned into a single ALU. | 14:26 |
| Myrl-saki | (Just to clarify, `unsigned_compare` should be `'x` there, in hindsight. | 14:26 |
| Myrl-saki | For the '0 cases. | 14:26 |
| Myrl-saki | tnt: Right now I'm targeting Gowin/Tang Nano 9k. | 14:27 |
| Myrl-saki | Okay, so I was able to skip the `and` gate by using the 'x. | 14:28 |
| Myrl-saki | Ah. | 14:29 |
| Myrl-saki | I think I understand what you mean by can't be a single ALU now. | 14:29 |
| Myrl-saki | Hm | 14:29 |
| lofty | ...I think I also just noticed a flaw in `synth_gowin` which does not help | 14:30 |
| Myrl-saki | I'm guessing that there's parameters which `show` doesn't show. | 14:31 |
| Myrl-saki | https://i.imgur.com/RNtvUvn.png | 14:31 |
| Myrl-saki | This is what it generates when I use `$signed(ra) < $signed(rb)` instead. | 14:32 |
| Myrl-saki | Which makes me think that maybe Yosys could merge them, because I can just replace `1` with `mode`, because it's only valid when `mode` is 1. | 14:32 |
| lofty | If you run `write_verilog` in a shell when stepping through commands you can get a reasonable idea of what Yosys is thinking | 14:33 |
| Myrl-saki | Oohh thanks. I think it's really just the signedness difference. Hmm. | 14:35 |
| Myrl-saki | `if (node->is_signed == is_signed && node->invert_b && node->c == State::S1)` | 14:40 |
| Myrl-saki | I wonder if this is actually required. | 14:40 |
| Myrl-saki | I mean, it's also not trivial to just change the checks. | 14:40 |
| lofty | Easiest way to answer that is to remove it and then run the Yosys test suite | 14:41 |
| Myrl-saki | Thanks. I'll do that. It'd be nice to make a PR if I figure this out. | 14:43 |
| Myrl-saki | Yay. :) | 16:07 |
| Myrl-saki | I don't think there are tests in place to catch this yet. How do I name the test? https://github.com/YosysHQ/yosys/pull/3991 | 16:16 |
| Myrl-saki | Okay there for sure aren't tests, because turns out something's wrong with this. :( | 16:27 |
| Myrl-saki | How it looks now. :) https://i.imgur.com/e4C8qbs.png | 17:12 |
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