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| Myrl-saki | Why does yosys create this to scatter the bits for an enable pin? https://i.imgur.com/PzJgMMM.png | 02:01 |
|---|---|---|
| lofty | Myrl-saki: opt_clean -purge and try again :p | 02:04 |
| Myrl-saki | Thanks. :) That seems to work for most. | 02:05 |
| Myrl-saki | Though, that doesn't seem to be what I needed to fix. | 02:05 |
| Myrl-saki | I am getting this diagnostic: `$flatten\furv.$7$memwr$\r$furv.v:126$107_EN[31:0]$365` | 02:05 |
| Myrl-saki | Er, sorry. | 02:06 |
| Myrl-saki | `Module `top' contains feedback arcs through wires:` | 02:06 |
| Myrl-saki | And that's one example of it. | 02:06 |
| lofty | I would need more context than that then | 02:07 |
| Myrl-saki | Sure thing. I'll push my code. | 02:08 |
| lofty | I can't promise I'll take a look at it, given the time | 02:08 |
| Myrl-saki | https://github.com/adrianparvino/furv/blob/main/furv.v#L111-L135 | 02:10 |
| Myrl-saki | This one has a smaller diagnostic $flatten\furv.$0$memwr$\r$furv.v:125$106_EN[31:0]$135 | 02:10 |
| Myrl-saki | I'm not so sure what a "feedback arc" means. | 02:10 |
| Myrl-saki | FWIW, doing splitnets fixes this. | 02:11 |
| Myrl-saki | Ah, I can just splitnets on the modules that have this problem, and thne flatten. | 02:11 |
| Myrl-saki | Ah, seems like `share -force` gets it. | 02:22 |
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| Myrl-saki | Well, turns out it disappears because it removes the store lol | 04:35 |
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| Myrl-saki | jix: Hi, sorry. How exactly do I load the module afetr blackboxing it? | 15:27 |
| Myrl-saki | Is this on nextpnr or on yosys? | 15:27 |
| Myrl-saki | ERROR: Unable to place cell 'rom', no BELs remaining to implement cell type 'rom' | 15:27 |
| jix | Myrl-saki: you load the module into a separate design (see `help design`) and then run techmap with that design as cell library (`help techmap`) | 15:28 |
| Myrl-saki | Thanks. :) | 15:29 |
| jix | I can elaborate later, but I'm about to leave | 15:29 |
| Myrl-saki | Good enough for me. ^^ I just needed a hint. | 15:29 |
| jix | Might also be able to just read_verilog the rom.v after synth but I haven't tried that and that gives you less control over what passes to run on that module independent from the rest of the design | 15:32 |
| Myrl-saki | Ah! I found a | 15:32 |
| Myrl-saki | Yes! | 15:32 |
| Myrl-saki | That's exactly what I did. :D | 15:32 |
| Myrl-saki | Well kind of. I did it directly before synth, but after all my optimization passes. | 15:33 |
| Myrl-saki | Thanks, seems like I got it. | 15:41 |
| Myrl-saki | Wild, removing the ROM makes yosys infer block RAM (it says SPX9?). Computers never cease to amaze me. That aside, I think I got it working! :) | 15:47 |
| Myrl-saki | Testing in a bit. | 15:47 |
| Myrl-saki | Yes! | 15:47 |
| Myrl-saki | This is my .ys file. https://gist.github.com/adrianparvino/940e122141f7c8b07197bb0778dfe31f | 15:48 |
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| lofty | Myrl-saki: that's a rather peculiar synthesis script | 17:57 |
| Myrl-saki | I decided to just flatten and opt, and that produces way smaller than whatever I wrote. : X | 18:19 |
| Myrl-saki | 3700 vs 4300 | 18:19 |
| Myrl-saki | Though, 4300 vs 4700 if I opt without flatten. | 18:19 |
| Myrl-saki | With that said, there's probably :tm: bugs in my code, because my core is not responding to UART lol | 18:20 |
| Myrl-saki | So that could account for the missing LUTs. | 18:21 |
| Myrl-saki | But yeah, so I had an idea of how I wanted the compilation to look in mind, that's why I am compiling each module with their own specific settings. | 18:21 |
| Myrl-saki | 92405: Optimizing lut uart.rx_ack_MUX2_LUT5_S0_1_I0_LUT1_F (1 -> 0) | 18:28 |
| Myrl-saki | Does this mean it got replaced by a constant? | 18:28 |
| Myrl-saki | log(" Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs)); | 18:29 |
| Myrl-saki | Seems so :x | 18:30 |
| Myrl-saki | Hmm | 18:30 |
| Myrl-saki | Can things break from `share`? | 18:31 |
| jix | Myrl-saki: Without `-force` it shouldn't break things. | 19:14 |
| Myrl-saki | How about -aggressive? | 19:15 |
| jix | Myrl-saki: If it does what it says in the help message that shouldn't be able to break things, but it's been a while since I looked at share's source code and I haven't done much with it | 19:17 |
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