Sunday, 2023-10-01

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corecodeMyrl-saki: what does this calculation do?09:10
corecodeMyrl-saki: is this a common way to express this?09:11
corecodeMyrl-saki: can't you just look at the high bits of the address?09:11
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Guest99Is there anything wrong with this verilog code?11:42
Guest99It works fine in simulation (icarus) and various linters (verilator, verible)11:42
Guest99are happy with it. However, yosys errors during synthesis: registers.v:0:11:42
Guest99ERROR: Identifier `\i' is implicitly declared and `default_nettype is set to11:42
Guest99none.11:42
Guest99https://pastebin.com/vGisuDd611:42
tpbTitle: initial begin integer i; for (i = 0; i < 32; i++) begin memor - Pastebin.com (at pastebin.com)11:42
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loftyGuest99: that code by itself looks fine, though perhaps the `integer i` declaration needs to be moved outside the `initial` block?13:21
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Guest99lofty: that does fix it, but I wanted to limit to scope of i to avoid accidentally reusing it in a different loop elsewhere in the file. I found a better workaround by extracting the code to a task. It seems like maybe local declarations are not allowed in the always block. But I don't really understand why some tools accept it and others do not.13:42
gatecatanother workaround is probably to name the block (e.g. `initial begin: foo`)14:27
gatecatbut this does look like a yosys bug14:28
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