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| Myrl-saki | Is there a way to tell Yosys to not assume anything about the values? | 15:11 |
|---|---|---|
| Myrl-saki | Or rather, assume that all bit representations are valid or something. | 15:11 |
| Myrl-saki | Specifically, I have a rom which is populated by readmemh, and Yosys is apparently smart enough to dead code eliminate everything else based on the contents of the ROM. | 15:12 |
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| lofty | Myrl-saki: invariably the answer is "fix the bug in your code" :p | 16:29 |
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| tnt | lofty: Not sure there is a bug in the code ... | 16:35 |
| lofty | tnt: Yosys should not be able to optimise out an entire design if there isn't | 16:35 |
| tnt | lofty: not entire design ... but possibly some path because it sees the rom content never has that bit at 1 for instance. But maybe that rom content is meant to be replaced dynamically post PNR. | 16:36 |
| tnt | so it'd be nice if you could tell it "don't optimize anything based on the content of the ROM". | 16:36 |
| lofty | Yosys will pretty much always want to map a ROM to LUTs | 16:37 |
| tnt | yeah, which is another problem in itself ... | 16:38 |
| tnt | but maybe it accepts ram_style | 16:38 |
| tnt | Ideally for postpnr replace the content would be filled with random so it's "unlikely" that it find any content dependent optimization, but still would be nice to be sure. | 16:39 |
| jix | I'm not sure what optimizations in which passes are the issue here, but what should work in any case is to keep the rom in a separate module that's loaded as a blackbox during synth and then only afterwards you read the module contents with the rom in it | 16:40 |
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| Myrl-saki | Yosys is making ALUs for this: wire ram_select = addr - 256 < 256; // 256 <= addr && addr < 256 + 256; | 20:00 |
| Myrl-saki | Ah wait. | 20:00 |
| lofty | Comparisons are implemented in terms of ALUs | 20:00 |
| lofty | (with some exceptions for very small comparisons) | 20:01 |
| Myrl-saki | I think it's because I'm calling alumacc too early. | 20:01 |
| Myrl-saki | Mhm, though isn't this faster with just a bunch of LUTs? | 20:01 |
| lofty | With interconnect delay for LUTs compared to fast carry chain? hard to say. | 20:02 |
| Myrl-saki | Okay, I called alumacc later, after opt -fine -full, and with the commented version as the expression, and it now no longer uses ALUs. | 20:05 |
| Myrl-saki | Though, that's interesting though. | 20:06 |
| Myrl-saki | I think I see what you mean. A comparison would be both wide and deep, since it has to generate partials for each bits, and then it gets collected after. A dedicated carry chain could actually be faster. | 20:08 |
| Myrl-saki | I think? | 20:08 |
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| icee | I'm trying to make a workflow with yosys on edaplayground for my students to see decent diagrams of trivial multi-module things | 20:09 |
| icee | I'm using flatten in my .ys file; but I get bufs going to names of internal signals | 20:09 |
| icee | How can i get it to actually eliminate these internal wire names etc | 20:09 |
| icee | i've tried making sure keep attributes are unset (but could be screwing this up); i've tried clean | 20:10 |
| lofty | icee: opt_clean -purge | 20:10 |
| lofty | At least, if I'm remembering correctly | 20:11 |
| lofty | Myrl-saki: depending on the architecture you can also break down comparisons to be even more efficient than naive subtraction while still using the carry chain | 20:13 |
| icee | nice! one sec, let me try | 20:18 |
| icee | !! thank you | 20:19 |
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