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| Wolf0 | https://twitter.com/Wolf9466/status/1431324160379301889 -- I built an FPGA machine! | 00:57 |
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| futarisIRCcloud | https://news.ycombinator.com/item?id=28329731 | 01:58 |
| tpb | Title: Arm China Has Gone Rogue | Hacker News (at news.ycombinator.com) | 01:58 |
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| Wolf0 | _florent_: you have an FK33? | 13:05 |
| Wolf0 | I'm currently working on some developer documentation for it | 13:05 |
| Wolf0 | https://twitter.com/Wolf9466/status/1431606901045972993 | 13:50 |
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| _florent_ | Wolf0: yes I have one | 14:37 |
| Wolf0 | _florent_: do you happen to have any other US+ HBM parts? Working on documenting a lot of 'em | 14:40 |
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| kbeckmann | Hi! Is there an easy way to use LiteScope over UART? I don't have ethernet on my board but I could easily add a second UART, or even FullSpeed USB with a PMOD. litescope_cli.py seems to expect an etherbone connection. | 17:06 |
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| kbeckmann | Ah, I think I misunderstood how it all connects together. litescope_cli connects to the litex_server that runs locally that in turn connects to wishbone over UART/PCIe/Ethernet/...? | 17:13 |
| kbeckmann | Yeap, that was it.. Sorry for the noise :) | 17:23 |
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| jevinskie[m] | Yeah its so elegant I missed the same thing :) | 18:07 |
| jevinskie[m] | Ahh, no wonder litex_sim Ethernet is so wonky on Mac (along with weird routing issues) is that the tuntap drivers don’t support kqueue so libevent doesn’t get read callbacks. I’ve worked around it by setting a short timeout and blindly attempting a non-blocking read in the timer callback | 18:09 |
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| _florent_ | kbeckmann, jevinskie[m]: This can probably give you a better overview: | 19:23 |
| _florent_ | https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC | 19:23 |
| _florent_ | https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC | 19:23 |
| kbeckmann | Thanks, the wiki is great! I had somehow missed the litex_server part so I got a bit confused. | 19:27 |
| kbeckmann | Are there plans to add compression to LiteScope? | 19:28 |
| jevinskie[m] | RLE support has been discussed: https://github.com/enjoy-digital/litescope/issues/7 | 20:05 |
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| pftbest | Is there a way to run DDR init over etherbone? I need to debug it but vivado takes too long to compile with a new bootrom each time | 21:03 |
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| jevinskie[m] | Yeah litedram bench/ includes a rw “rom” so you can load it via the python script | 23:17 |
| jevinskie[m] | Well not a way to run ddr init over wishbone but it’s a way to avoid vivado compiles | 23:18 |
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