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| jevinskie[m] | Yay, I got etherbone sim working on Mac after fixing routing further and making a fake gateway ip on the tap | 00:09 |
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| kbeckmann | Ah, nice to see RLE being discussed earlier. Could be fun to take a stab at it at a later time. LiteScope is a really useful tool, helped me a lot! | 06:53 |
| kbeckmann | I have some custom gateware in my LiteX SoC where I want to log low bandwidth data over a longer time over UART. Is there a "proper way" to do this? I was thinking of performing wishbone writes to the UART peripheral, but it feels a bit clunky to do so. | 06:57 |
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| _florent_ | pftbest: as pointed by jevinskie[m], you can indeed have a look at the LiteDRAM benches | 07:33 |
| _florent_ | it's possible to recompile the BIOS, reload it and reboot the CPU with --load-bios | 07:33 |
| _florent_ | it's useful to develop/investigate with liblitedram | 07:33 |
| _florent_ | kbeckmann: for your purpose, you can also just have a register inside the FPGA and just read it regularly over litex_server/UART/Etherbone | 07:35 |
| _florent_ | or eventually add a FIFO in between if you want to look at specific events | 07:35 |
| kbeckmann | Thanks, I will do something like that. | 07:38 |
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| pftbest | _florent_, jevinskie[m]: good idea, thanks | 09:26 |
| pftbest | I'm trying to debug why this happens: https://dpaste.com/368M69KCZ.txt | 09:27 |
| pftbest | Where delay was 19, but it selected 10+-0 for some reason | 09:27 |
| leons | Am I correct in that litex_sim currently has no GPIO support? I'm thinking of adding it, as it would be a really good addition for my CI | 09:35 |
| leons | I'm currently thinking about strategies for usefully exposing this to external applications. I can think of either a sysfs-style GPIO FUSE file system or a ZeroMQ-socket which applications can connect to | 09:37 |
| leons | I think a message-based (potentially ZeroMQ) system could be nice, as its easy for other applications to attach to the simulation and interact with it. In the future one could even have a graphical application to visualize GPIOs etc. | 09:45 |
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| jevinskie[m] | Leon: You might take some inspiration from the openocd remote but bang ASCII socket protocol. It was super simple to interface with! https://gist.github.com/jevinskie/67acb9d8bdf286463950d243fd1e54e5 | 20:29 |
| jevinskie[m] | I think your idea of gpio control over a socket is great, btw :) | 20:31 |
| jevinskie[m] | DearPygui is a great way to visualize some registers or gpio in a few dozen lines of python. Only problem was the lack of multiple window/viewports a few months ago. | 20:33 |
| jevinskie[m] | My test bench published every register read/write value to a socket that the “Register Cockpit” GUI then rendered in CSR-ish format with a line per field value/name. | 20:36 |
| jevinskie[m] | https://imgpile.com/images/N3lu68.png | 20:41 |
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