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| _florent_ | tpw_rules: with Vivado 2018.2, make sure the pcie_s7.xci hasn't been updated with your previous attempts with a newer version of Vivado (so just make sure to revert all eventual LitePCIe changes) | 08:34 |
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| pftbest | _florent_: Hello. I am trying to port litex to a new Kintex 7 board, but I have some issue with DDR3. It behaves randomly, sometimes it works and passes memtest but sometimes it fails | 10:31 |
| pftbest | For example https://dpaste.com/DNERCLY3H.txt | 10:31 |
| pftbest | In this log first it works fine, then I type reboot and it fails | 10:32 |
| pftbest | Can you give some hint why it may behave this way? | 10:32 |
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| Melkhior | pftbest: in your second part (where it fails), m2 it picking b03 delays: 07+-00 | 15:15 |
| Melkhior | but the seventh value on line b03 is a zero | 15:15 |
| Melkhior | the pattern looks weird - I think the BIOS code expect the 1 to be contiguous and pick the median between first and last | 15:15 |
| Melkhior | so with such a pattern of alternating block of 0 and 1 (not-working and working), the BIOS might get confused | 15:17 |
| pftbest | hm, do you know what can cause zeroes to appear here& | 15:17 |
| Melkhior | normally 0 is when there has been an error, I believe | 15:17 |
| Melkhior | so it goes a bunch of wrong timings (zeroes), a small number of OK timings (1), then more wrong timings (more 0) | 15:18 |
| Melkhior | and the BIOS picks the middle of the sequence of 1 | 15:18 |
| Melkhior | but in your case it doesn't do that - no idea why, not an expert | 15:18 |
| Melkhior | but that probably explains why it sometimes work and sometimes not | 15:19 |
| Melkhior | I would expect the pattern to look more like those in <https://gitmemory.com/issue/enjoy-digital/litex/890/826936087> | 15:21 |
| tpb | Title: Pull request #884 seems to break nexys video sdram - litex (at gitmemory.com) | 15:21 |
| Melkhior | (even though that's for an issue, the pattern looks OK) | 15:21 |
| pftbest | I see, thanks | 15:23 |
| Melkhior | Maybe the memory is run too slow ? Kintex 7 are fast (and probably could take DDR4 instead of DDR3) | 15:24 |
| Melkhior | I had some issue at one point with a too-slow system causing memory issues... | 15:24 |
| pftbest | in my case the memory is on a sodimm module DDR3-1066 | 15:24 |
| Melkhior | perhaps try with 125 or 150 MHz sys_clf_freq | 15:24 |
| Melkhior | s/clf/clk/ | 15:24 |
| pftbest | So my options are 100 125 and 133 | 15:25 |
| pftbest | but in my tests it seem to behave worse on higher frequencies | 15:25 |
| Melkhior | You have outside constraints ? (Litex should be able to configure any sys_clk_freq) | 15:25 |
| Melkhior | (though sometimes you need multiple PLLs for various clocks if their frequency relationship is weird) | 15:26 |
| Melkhior | ouch | 15:26 |
| pftbest | well, any frequency from 100 to 133 should work I think, but those 3 I tried so far | 15:27 |
| pftbest | 133 is the max because the memory is 1066 | 15:27 |
| Melkhior | You have a L2 in there, could be a source of trouble (including endianess issue in the framebuffer), maybe try without it... | 15:31 |
| Melkhior | the L2 forces the use of a Wishbone interface instead of the direct access | 15:31 |
| Melkhior | shouldn't affect the BIOS 'training', but you never know ... | 15:32 |
| Melkhior | might be worth a try... | 15:32 |
| pftbest | I tried to set it to 0 | 15:32 |
| Melkhior | Beyond that sorry I don't know :-( | 15:32 |
| pftbest | It didn't help unfortunately | 15:32 |
| pftbest | I can try to modify bios to make it find the longest sequence of 1 | 15:33 |
| Melkhior | Yes, but that might be a symptom of something else | 15:33 |
| Melkhior | Hopefully _florent_ will have better suggestions | 15:34 |
| Melkhior | Good luck... | 15:34 |
| pftbest | Melkhior: but it won't help in this case https://dpaste.com/8ZVFACMZD.txt | 15:35 |
| pftbest | where I get no 1 at all | 15:35 |
| pftbest | I'm not sure how it can vary so much between reboot | 15:35 |
| Melkhior | yes, no 1 is definitely bad... | 15:37 |
| Melkhior | The lack of 1 after 'Cmd/Clk' is also suspicious | 15:37 |
| pftbest | Do you know what is "Cmd/Clk scan"? | 15:39 |
| Melkhior | no, don't think my board did that | 15:40 |
| Melkhior | it's definitely in the BIOS | 15:41 |
| Melkhior | in sdram_write_leveling | 15:44 |
| Melkhior | maybe you can try a wider range than 0-16 and see what happens ? | 15:44 |
| Melkhior | You can also try to set SDRAM_WRITE_LEVELING_CMD_DELAY_DEBUG, maybe it will suggest something... | 15:48 |
| Melkhior | Seems your issue is above my skill level, sorry :-( | 15:48 |
| pftbest | Melkhior: I looked at the datasheet for my memory http://88.99.85.67:1337/Screenshot%202021-08-27%20at%2018.48.39.png | 15:49 |
| pftbest | Maybe I have to change CL CWL | 15:50 |
| pftbest | Or try sysclk lower than 100 | 15:50 |
| pftbest | because with CL-6 CWL-5 it seems 100 is an upper limit | 15:51 |
| Melkhior | Yes you could try 7/6, it the 2.5/3.3 is the min/max cycle time then it's 300->400 Mhz and with 100 Mhz sys_clk, the 4x is at 400 Mhz | 15:53 |
| Melkhior | 90 MHz would be in the middle of the range for 6/5 | 15:54 |
| pftbest | I'll try | 15:55 |
| Melkhior | cl / cwl are in get_ddr3_phy_init_sequence I think (litedram/litedram/init.py) | 15:56 |
| Melkhior | mmm, weird that you get 6/5 | 15:59 |
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| Melkhior | Default for 1066 is 7/6 https://github.com/enjoy-digital/litedram/blob/80398a8a15405b6958455bfa3c2beb500a459103/litedram/common.py#L44-L45 | 16:00 |
| Melkhior | ... but that might be based on the 'live' frequency, not that of the chip | 16:01 |
| pftbest | 90MHz 6/5 didn't help: https://dpaste.com/GLAG94UXB.txt | 16:19 |
| pftbest | Now will try to change CL | 16:19 |
| Melkhior | Interestingly, still loads of 0 for Cmd/Clk, but only 6 taps so something changed | 16:25 |
| pftbest | Melkhior: 6/7 still failed but Cmd has more 1 now https://dpaste.com/HQTFM3VYC.txt | 16:45 |
| Melkhior | Hehe and you went for higher frequency as well | 16:51 |
| Melkhior | m6 is a complete failure though - nothing worked | 16:51 |
| Melkhior | I think you should try 7/6 at 100 MHz... but I'm out of my depth here | 16:53 |
| Melkhior | Good luck again | 16:53 |
| pftbest | I'll try to find a different memory module, maybe the one I have is weird | 16:54 |
| Melkhior | Worth a shot if you have other modules handy | 16:55 |
| pftbest | I tried 7/6 @100 and it was the same, so I'll go disassemble my old laptop for some memory | 16:55 |
| _florent_ | pftbest: It seems the write DQ-DQS training is not done correctly on sometimes not done correctly on your board | 17:31 |
| _florent_ | can you try to force this to False: https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/s7ddrphy.py#L136 | 17:31 |
| pftbest | _florent_: I'll try | 17:32 |
| _florent_ | otherwise, be sure to configure the correct INTERNAL_VREF or DCI_CASCADE for the DDR3 bank | 17:34 |
| _florent_ | ex: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/digilent_genesys2.py#L162 | 17:34 |
| _florent_ | or https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/xilinx_kc705.py#L554 | 17:34 |
| _florent_ | If you are adapting from the MIG, be sure to use the same IO constraints | 17:34 |
| _florent_ | Is it your own board or a known development board? | 17:35 |
| pftbest | It is HPC-STLV7325. It has a reference design with MIG which works fine | 17:36 |
| pftbest | I copied kc705 platform and modified the pinouts | 17:36 |
| _florent_ | ok, can you share the .xdc for the DDR3/MIG? | 17:40 |
| pftbest | sure | 17:41 |
| pftbest | _florent_: http://88.99.85.67:1337/ddr_xdc.xdc | 17:45 |
| pftbest | and http://88.99.85.67:1337/k7325t_ddr3_1066_golden.xdc | 17:45 |
| _florent_ | ok, so DCI_CASCADE constraint is similar to the KC705 | 17:47 |
| pftbest | yes, it looks the same, the only difference is DQS pins are DIFF_SSTL15_T_DCI but for kc705 they are DIFF_SSTL15 | 17:50 |
| pftbest | I tried both but didn't observe any difference | 17:51 |
| pftbest | Also VCCAUX_IO is NORMAL in my case | 17:52 |
| _florent_ | ok, so you can try to disable the Write DQ/DQS training | 17:53 |
| _florent_ | it's a relatively new features and that's possible some corner cases are not handled correctly | 17:53 |
| pftbest | _florent_: I disabled the option but it still fails https://dpaste.com/HCXFQXKVK.txt | 18:14 |
| pftbest | _florent_: Is it ok that "Cmd/Clk scan" is mostly 0 ? | 18:15 |
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| pftbest | _florent_: I think this is the main issue in my case https://dpaste.com/F2AGR4ULR | 21:48 |
| tpb | Title: dpaste: F2AGR4ULR (at dpaste.com) | 21:48 |
| pftbest | It set delay to 0 because there was a glitch at the start | 21:48 |
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