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| poztit | Hi, is Yosys can format Verilog code ? I search the Yosys manual but found nothing revelant | 10:55 |
|---|---|---|
| poztit | like clang-format for example | 10:56 |
| Lofty | poztit: no, Yosys cannot format Verilog code | 11:41 |
| poztit | Lofty: ok, thank you for removing the doubt | 11:55 |
| Sarayan | poztit: I think slang can | 12:14 |
| Sarayan | iirc | 12:14 |
| Sarayan | https://github.com/MikePopoloski/slang | 12:14 |
| poztit | Yes but it's the big gun to achieve just formating ^^ | 12:21 |
| Sarayan | I don't see in which way yosys is a smaller gun :-) | 12:34 |
| poztit | Yeh true, in fact I use apio to develop on a TinyFPGA and it use Yosys to do the synthesis, so I would like to do the much I can with the tool already install | 12:39 |
| poztit | Sarayan: Do you use a formater for your projects ? | 12:46 |
| Sarayan | I avoid verilog :-) | 12:47 |
| Sarayan | I'm a nmigen fan | 12:47 |
| Sarayan | which has python formatting | 12:47 |
| poztit | Oh interesting ! | 12:48 |
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| Sarayan | make install doesn't install the cxxrtl headers? (or any header for the matter) | 15:39 |
| Sarayan | ah it does, how did the compiler miss them? | 15:41 |
| Sarayan | whitequark you are insane | 15:53 |
| Sarayan | clang++ -c -g -Wall -std=c++17 -O3 -I/people/galibert/share/yosys/include m68k.cc | 15:53 |
| Sarayan | m68k.cc:3191:264192: fatal error: bracket nesting level exceeded maximum of 256 | 15:53 |
| Sarayan | m68k.cc:3191:264192: note: use -fbracket-depth=N to increase maximum nesting level | 15:53 |
| Sarayan | wow, the line is >265K chars long | 15:55 |
| cr1901_modern | Sarayan: I pinged wq, since she's not in this room rn lol | 15:56 |
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| modwizcode | Sarayan: How are you generating the cxxrtl source for that module | 17:08 |
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