Monday, 2021-01-04

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Jay_jayjaywhy does instantiating `\$lut` not give the result as instantiating `SB_LUT4` ?17:31
LoftyJay_jayjay: it should, unless you're not matching the techmap rule17:32
LoftyOn the other hand we generally suggest *not* using \$lut directly17:32
Jay_jayjay  if (NATIVE) begin17:32
Jay_jayjay    SB_LUT4 #(.LUT_INIT(LUT)) main (.O(o),17:32
Jay_jayjay              .I0(a), .I1(b), .I2(c), .I3(d));17:32
Jay_jayjay  end17:32
Jay_jayjay  else begin17:32
Jay_jayjay    \$lut #(.WIDTH(4), .LUT(LUT)) main (.A({a, b, c, d}), .Y(o));17:32
Jay_jayjay  end17:32
Jay_jayjayhere's my code17:32
Jay_jayjayi checked, and it matches the rule17:32
Lofty.WIDTH should be 1617:33
LoftyAs in, 2^417:33
LoftyNot 417:33
Jay_jayjayLofty: I need specific low-level access to control timing17:33
LoftyJay_jayjay: ...suffice it to say in my experience that's almost certainly not what ends up happening17:33
Jay_jayjayoh, width should be 16? that's odd, usually its the # of inputs17:33
LoftyHmm17:34
LoftyNo, it should indeed be 417:34
Jay_jayjayLofty: if you really want the reason, I'm experimenting in asynchronous (unclocked) logic17:34
LoftyJay_jayjay: not with Yosys you aren't ;)17:34
Loftyasynchronous logic means logic loops17:35
Jay_jayjayyes, can't yosys handle those?17:35
LoftyWhich are Undefined Behaviour for Yosys17:35
LoftyThe entirety of the compiler assumes it will not encounter logic loops17:35
Jay_jayjaywell rn I'm trying a combinatorical logic thing, it should work17:35
LoftyIt is in fact an invariant of RTLIL that there are no combinational loops17:36
Jay_jayjayi need to verify my lut module to get anything useful17:36
LoftyYou could just use a right shift.17:36
LoftyWhich is going to reduce to a LUT of the right size17:36
Jay_jayjayalso, I don't think any tool, for that matter, supports async logic17:37
LoftySome do17:37
LoftyBut not Yosys17:37
Jay_jayjaybesides very specialized and probably deprecated tools17:37
daveshahYosys is fine with it so long as you stick to arch primitives17:37
daveshahie SB_LUT417:38
LoftyI suspect nextpnr will not time it though17:38
Jay_jayjayoh, that i use `--force`17:38
LoftySince it does sync-to-sync17:38
daveshahYes, that's correct nextpnr timing analysis won't work17:38
daveshahYou should use --ignore-loops not --force though to avoid overriding other unrelated issues17:39
Jay_jayjayyes, i've encountered the issue, but no timing analysis usually works anyway17:39
Jay_jayjayoh, thanks for the advice17:39
daveshahThe result it gives is meaningless once you have loops17:39
daveshah(very loosely, imagine its behaviour as breaking the loop in some arbitrary and undefined point)17:40
Jay_jayjayyes, I've expected that17:40
Jay_jayjayI don't care about timing analysis atm17:40
Lofty<Jay_jayjay>     \$lut #(.WIDTH(4), .LUT(LUT)) main (.A({a, b, c, d}), .Y(o)); <-- I should point out this is not equivalent with the direct SB_LUT4 instantiation17:42
Jay_jayjayyes, it optimizes it17:43
LoftyBecause the techmap rule would map that as .I0(d), .I1(c), ...17:43
Jay_jayjayoh, that17:43
Jay_jayjayI'll reverse the order, would that work?17:43
LoftyI might be a bit clueless, at times, but have a little faith17:43
LoftyReversing the order works17:43
daveshahNo, because $lut is not just techmapped to a LUT but also subject to optimisations in earlier phases17:43
Loftyhttps://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/cells_map.v#L2717:43
daveshahAnd those optimisations might be unsound once you take into account async behaviour, they aren't going to consider things like glitches or delays17:44
Jay_jayjayyes, I typically use SB_LUT4 for things that absolutely can't change, and \$lut for optimizable signals17:44
daveshahThat's reasonable enough17:45
daveshahBut yeah, as Lofty says be careful with the ordering17:46
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Jay_jayjayyes, I had to mess around with the ordering a lot17:48
Jay_jayjaytada! it works17:51
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philtorAnybody use the ghdl-yosys-plugin? Does it work reasonably well - how about missing features?23:03
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Loftyphiltor: it does work pretty well23:25
LoftyBut I'm not experienced enough to know what features are/aren't there23:25
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