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| benh | Any idea what this means ? | 02:25 |
|---|---|---|
| benh | ERROR: Assert `chunk.offset + chunk.width <= chunk.wire->width' failed in kernel/rtlil.cc:3553. | 02:25 |
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| benh | hrm... I think that's valid vhdl being translated into invalid verilog by ghdl-synth | 02:27 |
| benh | and now | 02:32 |
| benh | raised STORAGE_ERROR : stack overflow or erroneous memory access | 02:32 |
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| benh | ah fixed with updated ghdl :) | 02:38 |
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| ZipCPU | Glad you were able to figure it out! | 22:48 |
| ZipCPU | Wow ... that was a response to a comment from ... yesterday? Wow. I need to pay more attention to these time stamps. ;) | 22:49 |
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