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| ashfaq1717 | is there any channel for OpenSTA tool? on github, stackoverflow, reddit, irc? | 08:05 |
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| ashfaq1717 | is there any channel for OpenSTA tool? on github, stackoverflow, reddit, irc? | 09:15 |
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| Sarayan | 30% faster? Now that's interesting | 16:20 |
| ZirconiumX | Sarayan: ? | 16:33 |
| ZirconiumX | If you mean the performance work that's happened recently, yeah, Yosys is a fair bit faster now | 16:33 |
| Sarayan | https://twitter.com/whitequark/status/1252270371954450433 | 16:34 |
| whitequark | Sarayan: if you are directly poking posedge_p_clk it will not apply to you | 16:34 |
| Sarayan | wq: I wasn't, there was too many caveats, so I'm using the slow, safe version | 16:35 |
| whitequark | what it does mean is that some designs that would previously converge in >1 delta cycle for no good reason, now always converge in 1 delta cycle | 16:35 |
| whitequark | ah | 16:35 |
| whitequark | then it very much may apply to you | 16:35 |
| whitequark | I am slowly getting to the point where those caveats may be automatically checked | 16:35 |
| Sarayan | I know that my designs can be fully converged in one delta cycle | 16:35 |
| Sarayan | up to this point at least | 16:36 |
| whitequark | how many do they currently take? | 16:36 |
| Sarayan | Dunno. Suspect one, I do nothing weird | 16:36 |
| whitequark | three, if you don't do anything weird | 16:36 |
| Sarayan | ok | 16:36 |
| whitequark | one to propagate the clock pulse, one to propagate the *results* of the posedge, one to determine that the design converged | 16:37 |
| Sarayan | :-) | 16:37 |
| Sarayan | fuck, need to recompile yosys | 16:37 |
| Sarayan | yosys: error while loading shared libraries: libffi.so.6: cannot open shared object file: No such file or directory | 16:37 |
| whitequark | in theory, this can be reduced to just one, while remainign fully safe | 16:37 |
| whitequark | the patch i mentioned on twitter makes it always 3 | 16:37 |
| whitequark | instead of "usually 3 but sometimes *far* more" | 16:38 |
| Sarayan | urgh, I have slang in there, compile takes even longer | 16:38 |
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| Sarayan | argh, the interface changed | 16:44 |
| whitequark | of what? | 16:44 |
| Sarayan | main.cc:371:3: error: use of undeclared identifier 'value' | 16:44 |
| Sarayan | main.cc:183:1: error: use of undeclared identifier 'cxxrtl_design' | 16:45 |
| Sarayan | I guess I must be missing a namespace or something | 16:45 |
| whitequark | oh | 16:45 |
| whitequark | what -I flag do you use? | 16:45 |
| Sarayan | wait, I have bigger isues | 16:46 |
| whitequark | it should be -I <yosys-root> or -I /usr/local/share/yosys | 16:46 |
| Sarayan | yosys.cmd went wrong | 16:46 |
| whitequark | without the backends/cxxrtl/... | 16:46 |
| Sarayan | I had an empty c++ file generated for some reason | 16:47 |
| whitequark | h | 16:47 |
| whitequark | *ah | 16:47 |
| whitequark | btw, you can use separate compilation now | 16:47 |
| whitequark | -b 'cxxrtl -header' -o design.cc makes design.cc + design.h | 16:48 |
| Sarayan | oh, interesting | 16:48 |
| whitequark | so you don't have to spend time recompiling your stuff | 16:48 |
| Sarayan | I still have to recompile my stuff given the header changes | 16:48 |
| Sarayan | or at least pretends to | 16:48 |
| whitequark | that's true; I can make it so that it won't update the .cc or .h file if it is about to write the exact same thing inside | 16:49 |
| whitequark | hm, not the .cc file, but for the .h file, I can | 16:49 |
| Sarayan | doesn't the header have to change as soon as the internal state layout changes anyway? | 16:50 |
| whitequark | Sarayan: actually, if your design converges in 1 delta cycle, the header only contains registers | 16:52 |
| whitequark | ie sync signals | 16:52 |
| Sarayan | ok, my step sizes vary between 2 and 5 | 16:52 |
| whitequark | yes, then you'll benefit from the PR I am about to send | 16:52 |
| Sarayan | cool | 16:52 |
| whitequark | btw, can you show me your driver code again? | 16:52 |
| Sarayan | pushing the current state | 16:53 |
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| Sarayan | https://github.com/galibert/retrofpga/tree/master/overdrive | 16:53 |
| tpb | Title: retrofpga/overdrive at master · galibert/retrofpga · GitHub (at github.com) | 16:53 |
| Sarayan | via6522 has even simpler equivalent code | 16:53 |
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| Sarayan | yeah, via still compiles | 16:54 |
| whitequark | Sarayan: oof, that's some complex driver code | 16:55 |
| whitequark | ok, so here is what i wanted you to ensure, because i got it wrong in example code earlier | 16:55 |
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| Sarayan | overdrive yes | 16:55 |
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| Sarayan | check via6522, the cxxrtl aspects are identical | 16:55 |
| whitequark | you should *never* change inputs to a design at the same time as you trigger flops | 16:56 |
| whitequark | for example if you have posedge flops, at the step where p_clk goes 0->1, there should be *nothing else* going on | 16:56 |
| whitequark | you can think of it as the simulator version of setup/hold violation | 16:56 |
| Sarayan | so I should change values just before setting clk to 0? | 16:56 |
| whitequark | if you have just posedge flops, yep, that would be safe | 16:57 |
| whitequark | and also the fastest way to do it | 16:57 |
| Sarayan | posedge is default, right? | 16:57 |
| whitequark | yep | 16:57 |
| Sarayan | then I have everything posedge | 16:57 |
| Sarayan | I've learned my lesson, I have one clock, period | 16:57 |
| whitequark | then make sure you only change inputs on clk 1->0 | 16:57 |
| Sarayan | ok, I have to change both drivers then | 16:58 |
| whitequark | or your design will mysteriously break at some point later | 16:58 |
| whitequark | with some options, opt level, netlist and so on | 16:58 |
| whitequark | you know how race conditions look. you will get that. | 16:58 |
| whitequark | (or how setup/hold violations look...) | 16:59 |
| Sarayan | well, maybe it explains why I can't read stuff out of the via6522 (yeah right) | 16:59 |
| whitequark | possibly? | 16:59 |
| Sarayan | I was starting to be out of ideas, so maybe, even | 16:59 |
| Sarayan | I read after putting the clock back to 1 *and* stepping, right? | 17:00 |
| whitequark | yes | 17:01 |
| Sarayan | gah, I don't even know what the test is supposed to do anymore :-) | 17:02 |
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| Sarayan | I feel like I'm not on the correct branch | 17:07 |
| Sarayan | yeah, I was on a write_cxxrtl branch | 17:08 |
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