Tuesday, 2020-04-21

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az0reCan someone explain when exactly I should use `log_push()` and `log_pop()`?03:26
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ZirconiumXaz0re: when you want passes to be counted as substeps in the log09:06
ZirconiumXInstead of 1. A; 2. B; 3. C; 4. D09:07
ZirconiumXYou get 1. A; 1.1: B; 1.2: C; 1.3: D09:07
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lambdawhy is signed arithmetic in verilog such a giant pain again? from what I can tell, I only really have a chance of anything working if I first assign every input to a wire of width max(A, B, Y), then do the math, then assign it back to the output09:30
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ZirconiumXlambda: I think that's about what nMigen does09:40
ZirconiumXwhitequark: ^09:41
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az0reZirconiumX: Thanks.10:01
az0reBut how does that interplay with log_cmd_error?10:01
az0reIt just pops out of the whole stack?10:01
ZirconiumXYep10:04
az0reGotcha.  Thanks.10:07
ZirconiumXaz0re: log_cmd_error is unrecoverable (because there's a command syntax problem), so the stack doesn't mean much10:10
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lambdahm, truncating signed division is not easily optimized for power-of-two denominators (-3 / 4 = -0.75 = 0; simply shifting -3 right by 2 places gives -1 though). this is currently implemented wrong in opt_expr, too. I'm wondering, should it be replaced by a shift+add+reduce+mux or just not be optimized at all?13:16
whitequarki'm not really sure what kinds of practical designs use comb division in synthesis13:19
whitequarkwait13:19
lambdaFWIW the naive `x / (2^n) == x >> n` does hold true for all flooring divisions.13:19
whitequarkare you talking about a constant denominator?13:19
lambdayes, constant power-of-two denominator, opt_expr.cc:1506 is wrong for signed division (working on fixing that)13:21
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whitequarki'd say optimize it, since division by power of 2 is one of the cases people do expect to work13:21
whitequarkbut it is a weak preference13:22
lambdaalright, I'll see what I can do13:22
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tntSo, with cxxrtl, how would I generate a FST/LXT file containing all internal signals ?15:50
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ZirconiumXwhitequark: ^15:53
whitequarktnt: right now, cxxrtl designs aren't introspectible at all beyond writing C++ code that accesses the registers15:54
whitequarki'll fix this though, i have a plan that will let you inspect even (most) comb wires in optimized designs without *either* slowdown when debug is not used, *or* any sort of <value optimized out> bullshit15:55
whitequarkare you interested in *every* internal signal, even yosys $\d+ wires?15:55
whitequarkor just all public regs? all public regs and wires? (in verilog terms)15:56
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tntReally I just care about the 'wire/reg' that appear in my verilog code.16:04
tntAnd I can do without 'memories' since those take a insane amount of space with little benefits in most cases.16:05
tntIdeally if there is one I want traced I'd be able to mark it as such.16:05
whitequarktnt: what about... being able to request tracing any set of signals you want, at runtime, with no overhead if you aren't tracing any signals?16:05
whitequark(or memories for that matter)16:06
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whitequark(actually, i can emit delta compressed memories trivially, if the format supports them)16:06
tnttbh, for me at least changing at runtime doesn't matter much. I just dump everything and inspect in gtkwave to find the issue. I wouldn't want to have to re-run the sim each time I want to inspect another module.16:09
whitequarkah i see16:09
whitequarkthe main benefit would be that you could have e.g. `--debug` as an option in your test code that activates such a mode16:09
whitequarkand runs fast otherwise16:09
tntyeah, that's definitely useful, run with 'file output' to do spot checks and if output is not as expected dive-in. And some way to include/exclude modules as well. Most testbench include way more than the DUT and I don't necessary need to trace all the support code.16:15
whitequarkshould be fairly easy. the main problem would be including/excluding modules in flattened designs. but solvable too.16:16
tntwell the signals should have some names based on hierarchy anyway so just some regexp match would be fine.16:19
whitequarkurgh :S16:19
whitequarki mean sure i guess, something you could implement yourself16:20
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ZirconiumXwhitequark: Is it feasible to use bugpoint to debug something other than Yosys?17:14
whitequarkZirconiumX: it hardcodes some yosys args at the moment17:16
whitequarkbut you could easily modify it, i think17:16
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ZirconiumXI'm currently trying to use creduce to debug a Quartus ICE, and I think bugpoint being RTL-aware is going to be much more efficient than creduce getting lucky17:19
whitequarksure, i think you could modify run_yosys17:20
whitequarkbe aware that bugpoint expects the synthesizer to be fast. it... is likely to not work so well with quartus17:20
ZirconiumXSometimes Quartus outpaces synth_intel_alm, somehow17:20
whitequarkinteresting. even including startup cost?17:21
ZirconiumXWarm filesystem caches17:22
ZirconiumXCold caches mean Quartus gets destroyed17:22
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ZirconiumXIs it okay to put `run_pass("write_verilog <...>")` within run_yosys? As in, will that work with the passed-in design or does some work have to be done before then?17:27
whitequarkuhhh good question17:27
ZirconiumXAh, run_pass takes in an RTLIL::Design17:27
ZirconiumXThat'll probably work17:28
whitequarkyep17:28
ZirconiumXWell, I hacked bugpoint and now I'm getting an assert from Yosys (which I've also seen from other bugpoint runs but not been able to test)17:48
ZirconiumX"ERROR: Assert `refcount_modules_ == 0' failed in kernel/rtlil.cc:605"17:49
mwkthat one means you're manipulating the module list while simultanously iterating over it17:50
mwk.. specifically, removing a module17:50
ZirconiumXWhich bugpoint does17:50
ZirconiumXhttps://github.com/YosysHQ/yosys/blob/master/passes/cmds/bugpoint.cc#L136-L14417:51
tpbTitle: yosys/bugpoint.cc at master · YosysHQ/yosys · GitHub (at github.com)17:51
mwkthat's not supposed to happen17:51
mwk... how did that ever work17:52
mwkanyway, the usual pattern is to create a "modules to be removed" list in the loop, then make a second loop that actually removes them17:52
mwkI can make a patch if you want17:53
ZirconiumXYes please17:53
ZirconiumXIn the meantime I'll comment out the assert even though it's technically buggy17:53
mwk... do we have *any* bugpoint tests in yosys at all17:54
ZirconiumXI'm not sure how you'd test it as such, but it should definitely have them17:54
mwkZirconiumX: try mwk/bugpoint-fix17:57
mwk*UNTESTED*17:57
ZirconiumXAnd of course a git commit results in Yosys unnecessarily building everything17:59
ZirconiumXaaaagh17:59
ZirconiumXs/Yosys/make/17:59
mwk... there's been a good amount of PRs merged in the last few hours17:59
mwkincluding mine, which modifies kernel/rtlil.h18:00
ZirconiumXmwk: Still breaks18:08
mwk... how18:09
ZirconiumXBecause bugpoint does it again a few lines down18:09
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ZirconiumXin the `if (cells)` block18:09
mwkfuck.18:09
mwkalright, this will be a bigger PR18:09
ZirconiumXAnd for most of the other fix passes18:10
mwkupdated (force push)18:11
ZirconiumXUh, mwk18:12
ZirconiumXI'm totally expecting this to break somehow18:13
mwknonono, this will work18:14
mwkThis Time For Sure!18:14
ZirconiumXIronically it takes longer for write_verilog to do its job than for Quartus to crash on the input18:14
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mwk... that's a bit worrying18:14
ZirconiumXIt's kinda doing okay so far18:45
ZirconiumXI think hacking bugpoint was the right idea, as opposed to creduce18:46
ZirconiumXOn the other hand, it's removing a cell at a time18:46
ZirconiumXAnd there are 2950 of them :P18:46
ZirconiumXAt a rate of about 75 cells in 20 minutes19:05
ZirconiumXIs about 13 hours19:05
lambdahm, makes me wonder if patching in a binary search would be quicker overall :p19:06
ZirconiumXMaybe, but bugs like these are generally quite finicky to find19:07
lambdatrue, but it might help narrow it down significantly19:07
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ZirconiumXOn the plus side, it'll speed up as more cells get pruned19:09
ZirconiumXBecause it has to spend less time on it all19:09
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