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| az0re | Can someone explain when exactly I should use `log_push()` and `log_pop()`? | 03:26 |
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| ZirconiumX | az0re: when you want passes to be counted as substeps in the log | 09:06 |
| ZirconiumX | Instead of 1. A; 2. B; 3. C; 4. D | 09:07 |
| ZirconiumX | You get 1. A; 1.1: B; 1.2: C; 1.3: D | 09:07 |
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| lambda | why is signed arithmetic in verilog such a giant pain again? from what I can tell, I only really have a chance of anything working if I first assign every input to a wire of width max(A, B, Y), then do the math, then assign it back to the output | 09:30 |
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| ZirconiumX | lambda: I think that's about what nMigen does | 09:40 |
| ZirconiumX | whitequark: ^ | 09:41 |
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| az0re | ZirconiumX: Thanks. | 10:01 |
| az0re | But how does that interplay with log_cmd_error? | 10:01 |
| az0re | It just pops out of the whole stack? | 10:01 |
| ZirconiumX | Yep | 10:04 |
| az0re | Gotcha. Thanks. | 10:07 |
| ZirconiumX | az0re: log_cmd_error is unrecoverable (because there's a command syntax problem), so the stack doesn't mean much | 10:10 |
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| lambda | hm, truncating signed division is not easily optimized for power-of-two denominators (-3 / 4 = -0.75 = 0; simply shifting -3 right by 2 places gives -1 though). this is currently implemented wrong in opt_expr, too. I'm wondering, should it be replaced by a shift+add+reduce+mux or just not be optimized at all? | 13:16 |
| whitequark | i'm not really sure what kinds of practical designs use comb division in synthesis | 13:19 |
| whitequark | wait | 13:19 |
| lambda | FWIW the naive `x / (2^n) == x >> n` does hold true for all flooring divisions. | 13:19 |
| whitequark | are you talking about a constant denominator? | 13:19 |
| lambda | yes, constant power-of-two denominator, opt_expr.cc:1506 is wrong for signed division (working on fixing that) | 13:21 |
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| whitequark | i'd say optimize it, since division by power of 2 is one of the cases people do expect to work | 13:21 |
| whitequark | but it is a weak preference | 13:22 |
| lambda | alright, I'll see what I can do | 13:22 |
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| tnt | So, with cxxrtl, how would I generate a FST/LXT file containing all internal signals ? | 15:50 |
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| ZirconiumX | whitequark: ^ | 15:53 |
| whitequark | tnt: right now, cxxrtl designs aren't introspectible at all beyond writing C++ code that accesses the registers | 15:54 |
| whitequark | i'll fix this though, i have a plan that will let you inspect even (most) comb wires in optimized designs without *either* slowdown when debug is not used, *or* any sort of <value optimized out> bullshit | 15:55 |
| whitequark | are you interested in *every* internal signal, even yosys $\d+ wires? | 15:55 |
| whitequark | or just all public regs? all public regs and wires? (in verilog terms) | 15:56 |
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| tnt | Really I just care about the 'wire/reg' that appear in my verilog code. | 16:04 |
| tnt | And I can do without 'memories' since those take a insane amount of space with little benefits in most cases. | 16:05 |
| tnt | Ideally if there is one I want traced I'd be able to mark it as such. | 16:05 |
| whitequark | tnt: what about... being able to request tracing any set of signals you want, at runtime, with no overhead if you aren't tracing any signals? | 16:05 |
| whitequark | (or memories for that matter) | 16:06 |
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| whitequark | (actually, i can emit delta compressed memories trivially, if the format supports them) | 16:06 |
| tnt | tbh, for me at least changing at runtime doesn't matter much. I just dump everything and inspect in gtkwave to find the issue. I wouldn't want to have to re-run the sim each time I want to inspect another module. | 16:09 |
| whitequark | ah i see | 16:09 |
| whitequark | the main benefit would be that you could have e.g. `--debug` as an option in your test code that activates such a mode | 16:09 |
| whitequark | and runs fast otherwise | 16:09 |
| tnt | yeah, that's definitely useful, run with 'file output' to do spot checks and if output is not as expected dive-in. And some way to include/exclude modules as well. Most testbench include way more than the DUT and I don't necessary need to trace all the support code. | 16:15 |
| whitequark | should be fairly easy. the main problem would be including/excluding modules in flattened designs. but solvable too. | 16:16 |
| tnt | well the signals should have some names based on hierarchy anyway so just some regexp match would be fine. | 16:19 |
| whitequark | urgh :S | 16:19 |
| whitequark | i mean sure i guess, something you could implement yourself | 16:20 |
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| ZirconiumX | whitequark: Is it feasible to use bugpoint to debug something other than Yosys? | 17:14 |
| whitequark | ZirconiumX: it hardcodes some yosys args at the moment | 17:16 |
| whitequark | but you could easily modify it, i think | 17:16 |
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| ZirconiumX | I'm currently trying to use creduce to debug a Quartus ICE, and I think bugpoint being RTL-aware is going to be much more efficient than creduce getting lucky | 17:19 |
| whitequark | sure, i think you could modify run_yosys | 17:20 |
| whitequark | be aware that bugpoint expects the synthesizer to be fast. it... is likely to not work so well with quartus | 17:20 |
| ZirconiumX | Sometimes Quartus outpaces synth_intel_alm, somehow | 17:20 |
| whitequark | interesting. even including startup cost? | 17:21 |
| ZirconiumX | Warm filesystem caches | 17:22 |
| ZirconiumX | Cold caches mean Quartus gets destroyed | 17:22 |
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| ZirconiumX | Is it okay to put `run_pass("write_verilog <...>")` within run_yosys? As in, will that work with the passed-in design or does some work have to be done before then? | 17:27 |
| whitequark | uhhh good question | 17:27 |
| ZirconiumX | Ah, run_pass takes in an RTLIL::Design | 17:27 |
| ZirconiumX | That'll probably work | 17:28 |
| whitequark | yep | 17:28 |
| ZirconiumX | Well, I hacked bugpoint and now I'm getting an assert from Yosys (which I've also seen from other bugpoint runs but not been able to test) | 17:48 |
| ZirconiumX | "ERROR: Assert `refcount_modules_ == 0' failed in kernel/rtlil.cc:605" | 17:49 |
| mwk | that one means you're manipulating the module list while simultanously iterating over it | 17:50 |
| mwk | .. specifically, removing a module | 17:50 |
| ZirconiumX | Which bugpoint does | 17:50 |
| ZirconiumX | https://github.com/YosysHQ/yosys/blob/master/passes/cmds/bugpoint.cc#L136-L144 | 17:51 |
| tpb | Title: yosys/bugpoint.cc at master · YosysHQ/yosys · GitHub (at github.com) | 17:51 |
| mwk | that's not supposed to happen | 17:51 |
| mwk | ... how did that ever work | 17:52 |
| mwk | anyway, the usual pattern is to create a "modules to be removed" list in the loop, then make a second loop that actually removes them | 17:52 |
| mwk | I can make a patch if you want | 17:53 |
| ZirconiumX | Yes please | 17:53 |
| ZirconiumX | In the meantime I'll comment out the assert even though it's technically buggy | 17:53 |
| mwk | ... do we have *any* bugpoint tests in yosys at all | 17:54 |
| ZirconiumX | I'm not sure how you'd test it as such, but it should definitely have them | 17:54 |
| mwk | ZirconiumX: try mwk/bugpoint-fix | 17:57 |
| mwk | *UNTESTED* | 17:57 |
| ZirconiumX | And of course a git commit results in Yosys unnecessarily building everything | 17:59 |
| ZirconiumX | aaaagh | 17:59 |
| ZirconiumX | s/Yosys/make/ | 17:59 |
| mwk | ... there's been a good amount of PRs merged in the last few hours | 17:59 |
| mwk | including mine, which modifies kernel/rtlil.h | 18:00 |
| ZirconiumX | mwk: Still breaks | 18:08 |
| mwk | ... how | 18:09 |
| ZirconiumX | Because bugpoint does it again a few lines down | 18:09 |
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| ZirconiumX | in the `if (cells)` block | 18:09 |
| mwk | fuck. | 18:09 |
| mwk | alright, this will be a bigger PR | 18:09 |
| ZirconiumX | And for most of the other fix passes | 18:10 |
| mwk | updated (force push) | 18:11 |
| ZirconiumX | Uh, mwk | 18:12 |
| ZirconiumX | I'm totally expecting this to break somehow | 18:13 |
| mwk | nonono, this will work | 18:14 |
| mwk | This Time For Sure! | 18:14 |
| ZirconiumX | Ironically it takes longer for write_verilog to do its job than for Quartus to crash on the input | 18:14 |
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| mwk | ... that's a bit worrying | 18:14 |
| ZirconiumX | It's kinda doing okay so far | 18:45 |
| ZirconiumX | I think hacking bugpoint was the right idea, as opposed to creduce | 18:46 |
| ZirconiumX | On the other hand, it's removing a cell at a time | 18:46 |
| ZirconiumX | And there are 2950 of them :P | 18:46 |
| ZirconiumX | At a rate of about 75 cells in 20 minutes | 19:05 |
| ZirconiumX | Is about 13 hours | 19:05 |
| lambda | hm, makes me wonder if patching in a binary search would be quicker overall :p | 19:06 |
| ZirconiumX | Maybe, but bugs like these are generally quite finicky to find | 19:07 |
| lambda | true, but it might help narrow it down significantly | 19:07 |
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| ZirconiumX | On the plus side, it'll speed up as more cells get pruned | 19:09 |
| ZirconiumX | Because it has to spend less time on it all | 19:09 |
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