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| ashfaq1717 | how to convert NOR2 to NOR3 using techmap | 08:11 |
|---|---|---|
| daveshah | Do you mean one NOR2 to one NOR3? Techmap isn't for combining cells | 08:15 |
| whitequark | whee~ https://github.com/YosysHQ/yosys/pull/1963 | 08:16 |
| tpb | Title: cxxrtl: add support for simple and templated C++ black boxes by whitequark · Pull Request #1963 · YosysHQ/yosys · GitHub (at github.com) | 08:16 |
| ashfaq1717 | i have replaced nor 3 to combinations of nor 2 similarly I want to do vice versa | 08:17 |
| daveshah | extract is intended to be the opposite of techmap | 08:18 |
| ashfaq1717 | can you please write me the verilog code for extract map nor2 nor3 | 08:20 |
| ashfaq1717 | can I put this on github? | 08:28 |
| ashfaq1717 | module NOR3X1(input A, B, C, output Y);wire first_output;NOR2X1 first(.A(A), .B(B), .Y(first_output));NOR2X1 second(.A(first_output), .B(C), .Y(Y));endmodule | 08:29 |
| ashfaq1717 | this was nor3 to nor , I want a code for nor2 to nore3 | 08:29 |
| daveshah | What happens when you do extract with that file? | 08:30 |
| ashfaq1717 | I don't know exact syntax how I connect signals of nor2 to nor3 as I done for the above, I want a file which can do this using extract or techmap | 08:34 |
| ashfaq1717 | can I extract with the same file? | 08:35 |
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| ZirconiumX | ashfaq1717: that's what daveshah is asking you to do | 08:40 |
| ZirconiumX | Besides, couldn't you at least thank me for that code? | 08:40 |
| ZirconiumX | Congrats, whitequark | 08:41 |
| whitequark | thnks! | 08:42 |
| ashfaq1717 | when I use extract map with the above file it says 0 matches found it means we can't extract with the same file | 08:46 |
| ashfaq1717 | thank u ZirconiumX but I couldn't understand your code | 08:46 |
| ZirconiumX | ashfaq1717: how come? You literally straight-up copied it | 08:48 |
| ZirconiumX | https://github.com/YosysHQ/yosys/issues/1891#issuecomment-612003712 | 08:48 |
| tpb | Title: How to convert one cell to a combination of other cells? · Issue #1891 · YosysHQ/yosys · GitHub (at github.com) | 08:48 |
| ashfaq1717 | brother its Ok, it replaces the cells nor3 to nor2 I have checked it, but doing vice versa with extract it dosn't replace nor2s to nor 3 | 08:50 |
| * ZirconiumX sighs in being non-binary | 08:51 | |
| ashfaq1717 | any solution? | 08:54 |
| ZirconiumX | I've never used extract because I've never needed to use extract | 08:55 |
| ashfaq1717 | its Ok. any one else? | 08:56 |
| ZirconiumX | The thing is, by the time you need to use extract it is too late to do the thing you want to, generally | 08:56 |
| ZirconiumX | It's far better to use techmap to break high-level things down into what you want, than to use extract to build up into what you want | 08:57 |
| ashfaq1717 | can you give me a example | 08:59 |
| ZirconiumX | Say you want to make a specific adder | 08:59 |
| ZirconiumX | It's best to try mapping either $add or ideally $alu to build the adder out of the cells you want | 09:00 |
| ZirconiumX | Rather than try to build an adder from extracting half and full adders | 09:00 |
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| ashfaq1717 | how to convert DFFSR to DFF_P or DFF_N? what are benifits of doing so while Yosys automatically map to DFFSR? | 10:27 |
| ZirconiumX | ashfaq1717: dffsr2dff | 10:28 |
| ashfaq1717 | yup | 10:28 |
| daveshah | That's been removed | 10:28 |
| ZirconiumX | And the benefits are that the DFF cells are simpler, use less area and need less routing. | 10:29 |
| daveshah | opt_rmdff does everything it did | 10:29 |
| ZirconiumX | Since I'm on my phone I don't have access to the latest docs, and Claire's only get regenerated when there's a major release | 10:29 |
| ashfaq1717 | from where can i get dffsr2dff file | 10:37 |
| ZirconiumX | ashfaq1717: since opt_rmdff replaces it, use opt_rmdff instead | 10:38 |
| ashfaq1717 | ok | 10:38 |
| ZirconiumX | Which is probably run by default, actually | 10:41 |
| mwk | whitequark: that isn't the pull request that you needed stable avail_parameters order for, right? | 10:41 |
| whitequark | mwk: nope, turns out i didn't need it after all | 10:45 |
| mwk | ok, fair enough :) | 10:46 |
| ashfaq1717 | please refer me dffsr2dff file I want to see the difference by using it | 10:47 |
| mwk | ashfaq1717: just dig it out from git, it was removed in https://github.com/YosysHQ/yosys/commit/38a0c30d65584335fee3e17f9075711853638ac3 | 10:50 |
| tpb | Title: Get rid of dffsr2dff. · YosysHQ/yosys@38a0c30 · GitHub (at github.com) | 10:50 |
| ashfaq1717 | hmm | 10:51 |
| mwk | but it really is just a subset of opt_rmdff | 10:54 |
| mwk | doing the same transform, but badly | 10:54 |
| ashfaq1717 | i synthesis a simple alu, run yosys script after abc , i use extract map to replace gate cells with a macro add cell but same result found no match as for nor3 previously, | 10:59 |
| lambda | ashfaq1717: why do you want to do that though? | 10:59 |
| ashfaq1717 | I want to create an example how can I reduce the area by replacing many cells with a macro cell | 11:00 |
| ashfaq1717 | i am unable to synthesis a design to split it in gate cells and then map these cells to a macro cell | 11:23 |
| ashfaq1717 | kindly refer me some xample | 11:23 |
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