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| Sarayan | rtlil question: https://og.kervella.org/t.txt | 10:50 |
|---|---|---|
| Sarayan | extract of verilog follow by extract of rtlil (generated by the current frontend) | 10:50 |
| Sarayan | Why is there $0\cnt[20:0] ? | 10:50 |
| Sarayan | and if it's just "comb the intermediate value, then update on edge", why is there the assign $0\cnt[20:0] \cnt ? | 10:50 |
| daveshah | I'm not sure if it helps, but there is some background on this in the Yosys manual | 10:51 |
| whitequark | Sarayan: yup. please read the manual, if it's still not clear, i can go into detail | 10:52 |
| whitequark | but it would take a long time to write in a comprehensive way, so i'd prefer if you read the manual first | 10:52 |
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| ashfaq1717 | How to replace basic logic cells (Nand,Not etc ) with a macro cell (i.e. adder) | 12:41 |
| ashfaq1717 | If in a design there is an adder implemented by basic logic cells i.e. nand, not, etc, how can I identify that adder and replace with a macro adder cell to replace the logic cells? | 12:42 |
| mwk | first of all, what exactly are you trying to do? synthesis on some weird target that has an adder macro? reverse engineering an IC? | 12:46 |
| mwk | right now yosys only has the extract_fa pass which gives you full adder cells | 12:47 |
| mwk | it would probably be reasonably easy to make another pass that takes that and tries to chain them into proper $alu / $add / whatever chains | 12:47 |
| mwk | but there's no such thing yet | 12:47 |
| mwk | my main question is how did you end up with a netlist that only has basic logic cells | 12:48 |
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| Sarayan | ok, found it in the manual, and I see, it's just a default. But it's good to have a default, because you don't have to prove anything w.r.t completion of paths | 13:37 |
| Sarayan | and yeah, that part of the manual really clarifies things, thanks for pointing me to it | 13:38 |
| ZirconiumX | mwk: I'm assuming from the other issues that they've filed, they're doing ASIC synthesis | 13:39 |
| ZirconiumX | But they're gone now, so | 13:39 |
| mwk | I'm assuming as much, in which the right thing to do is recognize the damn $add cells *before* they end up as gates | 13:40 |
| mwk | hence my questions | 13:40 |
| ZirconiumX | Or possibly $alu | 13:46 |
| ZirconiumX | But anyway | 13:46 |
| daveshah | The advantage of mapping them at all for ASIC is much less than for FPGA | 13:46 |
| daveshah | With the current state of ASIC synthesis in Yosys, the lack of optimisations caused by the hard logic is probably costing more area than they save | 13:47 |
| daveshah | And there isn't really a timing advantage because between full adder standard cells and a full adder out of component cells afaik | 13:47 |
| daveshah | Certainly nowhere near the timing advantage from an FPGA carry chain | 13:48 |
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| ZirconiumX | So, at present, synth_intel_alm doesn't - can't, really - support RAM init | 14:34 |
| ZirconiumX | That makes e.g. nMigen designs with zero-initialised RAM get turned into flops | 14:35 |
| ZirconiumX | But I know that if LUTRAM isn't given an init parameter it defaults to zero | 14:36 |
| ZirconiumX | Suppose I mark the LUTRAM as initialisable (even though it's not) and if INIT=0 instantiate a LUTRAM anyway | 14:36 |
| ZirconiumX | How would I fall back to flops in case INIT != 0? | 14:36 |
| mwk | ... we need an "initializable, but only to 0" marker for rams | 14:37 |
| mwk | eg. xilinx ultraram is genuinely this way | 14:37 |
| daveshah | XCUP URAM also needs this | 14:37 |
| daveshah | yeah | 14:37 |
| daveshah | I need to check, but UltraPlus SPRAM might be too | 14:38 |
| ZirconiumX | Okay, it's useful to know I'm not alone here | 14:39 |
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| ZirconiumX | https://github.com/YosysHQ/yosys/issues/1958 | 14:54 |
| tpb | Title: memory_bram should have a "RAM initialises to zero" parameter · Issue #1958 · YosysHQ/yosys · GitHub (at github.com) | 14:55 |
| mwk | hmm, wasn't there an issue for that already... | 14:55 |
| mwk | huh, apparently not | 14:56 |
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| daveshah | The other outstanding issue is BRAM output register initialisation, which I tried to fix a few months ago but got too fed up with memory_bram | 15:14 |
| mwk | ... this seems to be a general problem with fixing BRAM things | 15:16 |
| mwk | you know what | 15:16 |
| mwk | I'm getting tired of this | 15:16 |
| mwk | as soon as I'm done with the current FF redesign saga, I'm starting the blockram inference redesign saga | 15:17 |
| mwk | so help me gods | 15:17 |
| * ZirconiumX snorts | 15:17 | |
| ZirconiumX | Good luck, mwk | 15:17 |
| lambda | she's offering to lose her sanity so we can keep ours - that's bravery right there | 15:27 |
| ZirconiumX | lambda: you already have to lose your sanity to have a hobby such as ours | 15:29 |
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| lambda | ZirconiumX: fair enough - but you can always bang your head against the wall just a little harder | 15:32 |
| ZirconiumX | lambda: Can I use your head instead? | 15:35 |
| * attie adds "Famous Last Words" to the playlist for this evening | 15:35 | |
| mwk | ... oh gods | 15:36 |
| mwk | you're going to torture me again, aren't you | 15:36 |
| attie | no, this one is a normal song | 15:36 |
| attie | also, I just discovered that MCR also did a song with that name | 15:37 |
| mwk | ... they did | 15:37 |
| attie | I was thinking of the Zeromancer song | 15:37 |
| lambda | ZirconiumX: and here I naively thought I could escape the depths of toolchain hell by pretending to just be a user... no chance, it pulls you right in | 15:37 |
| attie | it's just an inoffensive rock song | 15:38 |
| ZirconiumX | lambda: Are you reading my Yosys synth_intel_alm thread? :P | 15:42 |
| ZirconiumX | https://twitter.com/ZirconiumX/status/1251173509566550025 | 15:42 |
| lambda | ZirconiumX: oh dear | 15:44 |
| lambda | what a truly pleasant development environment | 15:44 |
| ZirconiumX | lambda: The main reason to use Yosys for synthesis instead of Quartus is that Yosys doesn't spend forever screaming at you for slight mistake | 15:51 |
| ZirconiumX | s | 15:51 |
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| mwk | https://github.com/YosysHQ/yosys/issues/1959 feel free to mention important things I forgot | 17:56 |
| tpb | Title: Memory inference redesign · Issue #1959 · YosysHQ/yosys · GitHub (at github.com) | 17:56 |
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| lambda | haha what even is this http://ix.io/2ir0 | 19:31 |
| lambda | reorder alll the bits | 19:31 |
| ZirconiumX | lambda: Did..did you just attach a PNG as a test file? | 19:32 |
| ZirconiumX | *text | 19:32 |
| lambda | huh? I just pushed a screenshot to ix.io, works fine when viewed in a browser here | 19:32 |
| ZirconiumX | Firefox presents it with text encoding | 19:32 |
| lambda | bleh | 19:32 |
| lambda | you're right, "Content-Type: text/plain", seems qutebrowser just completely ignores that and shows it as an image anyway, fun | 19:34 |
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| Sarayan | ;3A;3A/jmi | 22:20 |
| Sarayan | LN: What's the PMC? | 22:20 |
| Sarayan | gah | 22:20 |
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