| *** tpb has joined #yosys | 00:00 | |
| *** vidbina has joined #yosys | 00:14 | |
| *** emeb has quit IRC | 01:02 | |
| *** RicBent has quit IRC | 02:15 | |
| *** emeb_mac has quit IRC | 02:18 | |
| *** peepsalot has joined #yosys | 02:21 | |
| *** vidbina has quit IRC | 02:36 | |
| *** rohitksingh has quit IRC | 03:30 | |
| *** citypw has joined #yosys | 03:31 | |
| *** rohitksingh has joined #yosys | 03:31 | |
| *** az0re has quit IRC | 06:27 | |
| sensille | daveshah: one intermediate result: if i don't use the uppermost bit of the ram, yosys doesn't infer block ram, with the same reason that the read clock is 'async' (which it is not) | 07:59 |
|---|---|---|
| sensille | that insight doesn't help me with my full design, though (yet) | 07:59 |
| *** jakobwenzel has joined #yosys | 08:15 | |
| *** dys has quit IRC | 08:16 | |
| sensille | ok, i also found an assign to 0 for a lower layer output, which yosys did not complain about (or not enough). without that, i now get bram | 08:22 |
| *** fsasm has joined #yosys | 08:29 | |
| *** m4ssi has joined #yosys | 08:31 | |
| *** dys has joined #yosys | 09:09 | |
| *** twnqx has joined #yosys | 09:14 | |
| *** peepsalot has quit IRC | 09:38 | |
| *** az0re has joined #yosys | 10:32 | |
| *** peepsalot has joined #yosys | 10:43 | |
| *** rohitksingh has quit IRC | 11:08 | |
| *** develonepi3 has joined #yosys | 12:13 | |
| ZirconiumX | https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simlib.v#L529 <--- the `^ (Y ^ Y)` term seems very wrong to me; doesn't that simplify out entirely? | 13:09 |
| tpb | Title: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at github.com) | 13:09 |
| daveshah | ZirconiumX: not if Y contains 'x' bits | 13:11 |
| ZirconiumX | Ah, x-propagation | 13:11 |
| *** N2TOH has joined #yosys | 13:18 | |
| *** alexhw has joined #yosys | 14:07 | |
| *** twnqx has quit IRC | 14:25 | |
| *** X-Scale` has joined #yosys | 14:39 | |
| *** X-Scale has quit IRC | 14:41 | |
| *** X-Scale` is now known as X-Scale | 14:41 | |
| *** alexhw has quit IRC | 14:54 | |
| *** alexhw has joined #yosys | 14:58 | |
| *** twnqx has joined #yosys | 15:14 | |
| *** emeb has joined #yosys | 15:27 | |
| *** develonepi3 has quit IRC | 15:29 | |
| *** jakobwenzel has quit IRC | 15:47 | |
| *** fsasm has quit IRC | 16:12 | |
| *** X-Scale has quit IRC | 16:12 | |
| *** X-Scale` has joined #yosys | 16:14 | |
| *** X-Scale` is now known as X-Scale | 16:15 | |
| *** twnqx has quit IRC | 16:19 | |
| *** r_miller has joined #yosys | 16:32 | |
| r_miller | Can anyone help me interpret this report from nextpnr? https://pastebin.com/Xx8BhZVU Seems to be saying that resetn is assigned to a global buffer but taking 3.9ns to be routed a long way across the chip (5,2) -> (22,27). Is this right? | 16:36 |
| tpb | Title: Info: Promoting globals.. Info: promoting $abc$55324$n71 [reset] (fanout 358) - Pastebin.com (at pastebin.com) | 16:36 |
| *** citypw has quit IRC | 16:39 | |
| ZirconiumX | r_miller: that's precisely *because* it's a global buffer, I'd imagine. | 16:54 |
| ZirconiumX | ECP5 has GSR; if you don't care about portability use that instead of a power-on reset | 16:54 |
| r_miller | Sorry should have said: this is ice40. | 16:55 |
| ZirconiumX | iCE40 has pretty slow routing | 16:55 |
| ZirconiumX | Depends on the chip family though; what's the exact chip you're targeting? | 16:55 |
| r_miller | HX8k | 16:56 |
| ZirconiumX | Hmm. Let's ask daveshah | 16:56 |
| ZirconiumX | By the way, r_miller, when was the last time you updated your Yosys? | 16:56 |
| r_miller | Yesterday! | 16:56 |
| daveshah | The problem is that iirc the globals are only used for real flop reset signals, to avoid unroutability issues when they are driving LUTs | 16:56 |
| ZirconiumX | ...autoname isn't helping much, then | 16:57 |
| daveshah | and the path here seems to be a LUT input | 16:57 |
| daveshah | using an active high reset to match the hardware might help | 16:57 |
| r_miller | I noticed it says 'cen' not 'reset' on the promotion message. | 16:57 |
| daveshah | Indeed, looks like it is being promoted as a clock enable rather than a reset | 16:58 |
| r_miller | I'm using it like "always @(posedge clk) if (~resetn) begin ... end" | 16:58 |
| daveshah | You might have more success with `if (reset)` | 16:58 |
| r_miller | I've tried that too, but maybe I missed an instance somewhere? | 16:59 |
| daveshah | and if you are using a clock enable too, reset needs to be gated by it (so `if (cen) begin if (reset) ... else ... end`) | 16:59 |
| r_miller | Would the routing be quicker if I convinced yosys/nextpnr to treat it as a reset? | 17:00 |
| daveshah | Probably not that much so | 17:00 |
| daveshah | from memory the global buffer adds about 1ns anyway | 17:01 |
| daveshah | and there is the routing to the global buffer input too | 17:01 |
| r_miller | It's a delay generated internally by a counter, I guess I could have separate local ones instead of one global one. | 17:01 |
| *** citypw has joined #yosys | 17:03 | |
| *** m4ssi has quit IRC | 17:11 | |
| *** dys has quit IRC | 17:38 | |
| *** sfs1926 has joined #yosys | 17:39 | |
| *** rohitksingh has joined #yosys | 17:48 | |
| *** vidbina has joined #yosys | 17:49 | |
| *** citypw has quit IRC | 17:59 | |
| *** twnqx has joined #yosys | 18:06 | |
| *** anticw has quit IRC | 18:07 | |
| *** vidbina has quit IRC | 18:17 | |
| *** Xiretza is now known as lambda | 18:19 | |
| *** vidbina has joined #yosys | 18:20 | |
| *** sfs1926 has quit IRC | 18:25 | |
| *** vidbina has quit IRC | 18:46 | |
| *** vidbina has joined #yosys | 18:47 | |
| *** dys has joined #yosys | 18:57 | |
| *** lambda_ has joined #yosys | 18:58 | |
| *** lambda has quit IRC | 18:58 | |
| *** lambda_ is now known as lambda | 18:59 | |
| *** sfs1926 has joined #yosys | 19:11 | |
| *** fsasm has joined #yosys | 19:17 | |
| *** rohitksingh has quit IRC | 19:20 | |
| *** rohitksingh has joined #yosys | 19:35 | |
| *** rohitksingh has quit IRC | 19:49 | |
| *** Jybz has joined #yosys | 20:33 | |
| *** kristianpaul has quit IRC | 20:38 | |
| *** kristianpaul has joined #yosys | 20:39 | |
| *** fsasm has quit IRC | 21:01 | |
| *** az0re has quit IRC | 21:02 | |
| *** Jybz has quit IRC | 21:13 | |
| *** vidbina has quit IRC | 21:16 | |
| *** vidbina has joined #yosys | 21:18 | |
| *** klotz has joined #yosys | 21:30 | |
| *** rohitksingh has joined #yosys | 21:42 | |
| *** vidbina has quit IRC | 21:59 | |
| *** az0re has joined #yosys | 22:05 | |
| *** rohitksingh has quit IRC | 22:48 | |
| *** r_miller has quit IRC | 23:10 | |
| *** sfs1926 has quit IRC | 23:10 | |
| *** vidbina has joined #yosys | 23:32 | |
| *** rohitksingh has joined #yosys | 23:58 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!