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| awygle | daveshah: is "input with pullup" the expected default state of pins in the ECP5 as well | 05:30 |
|---|---|---|
| awygle | ? | 05:30 |
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| daveshah | awygle: no, it's input will pull down for ECP5 | 07:45 |
| awygle | ah, that squares with my observations | 07:46 |
| awygle | i solved my problem tho | 07:46 |
| awygle | my versa board came with the second channel on the ECP5 configured as a FIFO, not a UART | 07:46 |
| awygle | (which doesn't make any sense given how the board is routed but nvm) | 07:47 |
| daveshah | I've heard of EVN boards being shipped like this, but never Versas until now | 07:47 |
| awygle | it also doesn't have the descriptor that nmigen expected, fwiw | 07:49 |
| awygle | but it's pretty old. i got it something like 2 years ago. | 07:49 |
| sensille | I can't spot the mistake, yosys doesn't want to infer bram here: https://pastebin.com/rUJVBfth | 08:56 |
| tpb | Title: always @(posedge clk) begin dout <= ram[rdptr]; if (clr) begin - Pastebin.com (at pastebin.com) | 08:56 |
| sensille | Read port #0 is in clock domain !~async~. | 08:57 |
| sensille | altough it is explicitly registered | 08:57 |
| daveshah | Is there an initial value on dout? | 09:30 |
| sensille | yes | 09:31 |
| sensille | trying ... | 09:31 |
| sensille | nope, same without | 09:34 |
| sensille | full file: https://pastebin.com/VhCZ7Pyu | 09:35 |
| tpb | Title: `timescale 1ns / 1ps `default_nettype none /* * simple fifo. The next data - Pastebin.com (at pastebin.com) | 09:35 |
| daveshah | Seems to work fine here | 09:38 |
| sensille | strange | 09:41 |
| daveshah | Is this with default DATA_WIDTH and ADDR_WIDTH? if you overrode ADDR_WIDTH to be smaller Yosys might see it more efficient to use LUTRAM instead (but this would be a different message) | 09:57 |
| sensille | DATA_WIDTH=72, ADDR_WIDTH=9 | 10:00 |
| sensille | also it _says_ it doesn't use bram because "Read port #0 is in clock domain !~async~." | 10:01 |
| sensille | dunno if that's the real reason, though | 10:01 |
| sensille | same problem with another ram | 10:08 |
| sensille | i'll reduce the design to something where bram still gets inferred and work up from that later, thanks for testing | 10:12 |
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| janrinze | daveshah: using DP16KD i get the data after the clock. if i just use an array in verilog i can get the data before the clock. how does yoysys/nextpnr setup DP16KD to achieve that? | 13:18 |
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| janrinze | daveshah: does yoysys 'smartly' implement a write to the 'read address' using substitution? thus assuring that the data is available on the next clock? | 13:31 |
| tnt | janrinze: what do you mean before the clock ? | 13:38 |
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| janrinze | tnt: DP16KD has a clock | 13:42 |
| janrinze | tnt: with reg[15:0] memory[0:8191] you can do 'always@* out=memory[address] ; always@(posedge clk) memory[address]=in;' | 13:44 |
| tnt | yeah ... and that's not going to map to a DP16KD | 13:46 |
| janrinze | tnt: it actually does. | 13:46 |
| tnt | unless `address` is a register | 13:46 |
| tnt | and then yosys will "move" the register. | 13:46 |
| janrinze | address is a register | 13:46 |
| janrinze | tnt: 'move' as in using the read address as the detination register? | 13:47 |
| janrinze | oops 'destination' | 13:47 |
| tnt | it will use the input to the address register (instead of the ouptut) to actually feed the address input of the DP16K read side. | 13:47 |
| janrinze | tnt: yup | 13:48 |
| janrinze | tnt: but how can i infer the same? | 13:48 |
| tnt | ? | 13:48 |
| janrinze | tnt: with using the DP16K primitive? | 13:48 |
| tnt | That's not 'infer' ... 'infer' is letting yosys do it. | 13:48 |
| tnt | 'instanciate' is doing it 'manually'. | 13:49 |
| janrinze | okay.. how can i get the same behaviour that yosys does ? | 13:49 |
| tnt | Well you need to change your HDL ... | 13:49 |
| janrinze | using DP16K | 13:49 |
| tnt | if you only have access to 'address' register output, you can't. | 13:49 |
| janrinze | yosys can but i can't.. i see | 13:50 |
| tnt | yosys has access to the whole design and can mangle it like it wants. You can't do that ... | 13:50 |
| janrinze | the 'move' magic would be very nice to have. | 13:50 |
| janrinze | same for the output register, ifr i clock that in then it will be 'late' by one clock.. | 13:51 |
| tnt | yosys can add read bypass logic if need be. | 13:53 |
| janrinze | okay, yoysys can do some nice mapping and it will work on the proper clock transition. There aren't any verilog tricks to do the same, right? | 13:53 |
| tnt | well no ... you instanciate a blackbox, verilog has no clue what that black box does. | 13:54 |
| tnt | if it doesn't do what you need, tough luck, it's up to you to rewrite the logic around it so it fits your use case. | 13:55 |
| janrinze | tnt: does 'always@*' imply a 'move' ? | 14:02 |
| tnt | always @* descives combinatorial logic / asynchronous reads. | 14:04 |
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| RicBent | Hey there, is it ok if I ask an hardware related question here? | 19:31 |
| daveshah | Sure! | 19:31 |
| RicBent | alright :) | 19:31 |
| RicBent | I built this circuit: https://i.imgur.com/94IIuHh.png | 19:32 |
| RicBent | with an HX1K | 19:32 |
| RicBent | programming the FPGA via RPI is working | 19:32 |
| RicBent | programming the SPI flash also works | 19:32 |
| RicBent | but the FPGA doesn't seem to configure from the flash | 19:32 |
| RicBent | any obvious messup there? | 19:32 |
| daveshah | Are you connecting SS1 and SS2 when doing this? | 19:33 |
| RicBent | nope | 19:33 |
| daveshah | I think the iCE40 might need to drive flash chip select as it would be needed for framing | 19:34 |
| daveshah | SS on the iCE40 also needs to be pulled up to boot itself from flash, so R5 might be a problem | 19:34 |
| RicBent | ah, I see | 19:35 |
| RicBent | should've read the datasheet properly I guess :P | 19:35 |
| RicBent | still surprised this thing works at all | 19:37 |
| RicBent | https://i.imgur.com/rPJkzEg.jpg | 19:37 |
| RicBent | first PCB I ever did. also first SMD solder job | 19:37 |
| daveshah | Congrats! | 19:39 |
| tnt | GNDPLL must not be connected to ground. | 19:51 |
| tnt | See https://i.imgur.com/qQwqUo5.png | 19:54 |
| RicBent | welp, that isn't fixable anymore | 19:55 |
| RicBent | got it to configure from SPi though :D | 19:55 |
| tnt | You could always lift the pin(s) and reword that. | 20:05 |
| tnt | Just be aware of it if you have issues using the PLLs. | 20:05 |
| tnt | s/reword/rework/ | 20:06 |
| tnt | Board looks neatly laid out for a first PCB though. | 20:15 |
| RicBent | heh, thanks! | 20:15 |
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| RicBent | put my board on GitHub is anybody is interested: https://github.com/RicBent/Hisame | 21:06 |
| tpb | Title: GitHub - RicBent/Hisame: Development board for the Lattice iCE40 HX1K FPGA (at github.com) | 21:06 |
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