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| tnt | Am I mis-understanding how interface works : https://pastebin.com/dxq1PdiW ? | 00:06 |
|---|---|---|
| tpb | Title: [SystemVerilog] interface test( input wire clk, output wire [31:0] rdata ); - Pastebin.com (at pastebin.com) | 00:06 |
| tnt | "ERROR: Identifier `\wb.rdata' is implicitly declared and `default_nettype is set to none" | 00:07 |
| ZirconiumX | Is this a SV feature supported by Yosys, anyway? | 00:13 |
| tnt | Readme says "SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether ports are inputs or outputs are supported." | 00:16 |
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