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| twnqx | so... what do yosys and friends do with unused pins on an fpga? tristate, output, input? | 21:11 |
|---|---|---|
| daveshah | Totally unused? input with pullup, same as if the FPGA is not configured at all | 21:11 |
| daveshah | (for iCE40) | 21:11 |
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| mwk | twnqx: that does not depend on yosys, fyi; yosys doesn't even know what pins the fpga has | 21:13 |
| twnqx | that's what i was hoping for, great | 21:13 |
| twnqx | hence "and friends" :P not sure if part of nextpnr or icepack | 21:13 |
| twnqx | also, i just realized i actually have to figure out tristate buffers as my SPI bus is shared :/ | 21:14 |
| sensille | you can assign 'Z' to the signal | 21:15 |
| twnqx | uh. i am not quite sure that will correctly end up with a tristate-enabled SB_IO | 21:16 |
| mwk | assign pin = oe ? o : 1'bz; | 21:16 |
| mwk | that should do the trick | 21:16 |
| mwk | (and if not, report a bug) | 21:16 |
| twnqx | (and if not - magic smoke) :P | 21:16 |
| twnqx | actually, i should a) be able to test it nondestructively, and b) be able to see it in icepack's GUI, no? | 21:19 |
| twnqx | err nextpnr's | 21:21 |
| mwk | right | 21:21 |
| twnqx | except nextpnr insists on either the right device, or loading a json :( | 21:28 |
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| awygle | Is there anything better than yosys' dot graph output for visualizing synthesis results? | 22:06 |
| awygle | I thought I'd seen an interactive schematic thing at Latch-Up or one of those conferences | 22:06 |
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| awygle | oh there's an online demo of netlistsvg, that's not bad | 22:21 |
| twnqx | yeah, clearly doesn't work with just wire MISO = CS ? 1'bz : MOSI; - output follows mosi regardless of cs | 22:24 |
| mwk | twnqx: could you give me a reproducible test case? | 22:28 |
| twnqx | difficult as i use my own fpga + cpu system for the tests | 22:28 |
| mwk | you're literally claiming a single line example doesn't work | 22:31 |
| twnqx | i am removing everything else and boiling it down to that right now. | 22:31 |
| twnqx | https://gist.github.com/chrschmidt/6e90479cd0b8d27a419cab1f70184369 in this case, i observe MISO following MOSI regardless of CS | 22:34 |
| tpb | Title: gist:6e90479cd0b8d27a419cab1f70184369 ยท GitHub (at gist.github.com) | 22:34 |
| twnqx | unless i have a physical short between MISO and MOSI. | 22:36 |
| twnqx | in which case i doubt i could program the fpga, but still i'll check that | 22:36 |
| mwk | twnqx: a test case should include a command line | 22:37 |
| twnqx | updated | 22:39 |
| twnqx | i mean, i can't provide a command line for the physical test i am doing... | 22:40 |
| mwk | I know, I just want to see if yosys and/or nextpnr do something stupid | 22:41 |
| twnqx | i've seen others use inout for their tristate tests.. i should check with that | 22:42 |
| twnqx | though this is purely an output | 22:42 |
| mwk | try that, although it should work with an output | 22:43 |
| daveshah | At a glance, looks like nextpnr is dealing with the tristate there fine | 22:48 |
| daveshah | I'm assuming that your nextpnr is fairly recently built though? | 22:49 |
| twnqx | git head from some time yesterday | 22:50 |
| daveshah | No problem there | 22:50 |
| daveshah | Can you share the asc file you actually get? | 22:51 |
| twnqx | ... i'll check another IC's datasheet first | 22:51 |
| twnqx | are any pullup/pulldown involved in tristate? | 22:58 |
| daveshah | I think pullups should be disabled by default for used pins | 22:59 |
| twnqx | inverting the test sequence, it seems that a pretty strong (stronger than my cpu's pullup) keeper circuit is involved... | 23:01 |
| twnqx | and it's not following after all | 23:02 |
| twnqx | now to figure out if that level shifter is to blame | 23:02 |
| twnqx | i really should have deisgned the PCB with more test points :( | 23:04 |
| mwk | ... you have a level shifter on something where tristates are involved? | 23:04 |
| mwk | and pullups? | 23:04 |
| twnqx | automatic direction sensing & bidirectional. | 23:04 |
| mwk | oh god | 23:04 |
| twnqx | and no, the pullup is activated for the test only and not normally | 23:04 |
| mwk | that *never* ends well | 23:04 |
| twnqx | how else could i use 5V and 3.3V things on one SPI bus... | 23:05 |
| mwk | uhh, by using CS as output enable? | 23:06 |
| mwk | and a non-automatic level shifter | 23:06 |
| mwk | seriously, automatic direction sensing is the work of the devil | 23:06 |
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| twnqx | i did not have space for 3-4 level shifters :( | 23:09 |
| twnqx | but the txb0106 so far never caused issues | 23:10 |
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| twnqx | also, what's wrong with pullups? if all slaves on an SPI bus are in tristate, the master's input would float. that's never a good state. | 23:17 |
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| ZirconiumX | I think mwk's point is that *not* having the pullups ends poorly | 23:26 |
| mwk | pullups interfere badly with direction auto-detect | 23:29 |
| mwk | see glasgow revA/revB for an example | 23:29 |
| twnqx | especially if they are too strong | 23:29 |
| awygle | _having_ pull-ups with autosensing level shifters is not going to work out well | 23:30 |
| twnqx | yes, they act as keepers - so you don't really need them either | 23:30 |
| twnqx | i was misunderstanding the remark as "tristate and pullups don't match" | 23:30 |
| awygle | (also those level shifters tend to turn into oscillators if you sneeze on them) | 23:30 |
| awygle | (just to back up what mwk was saying) | 23:31 |
| twnqx | so far i never had issues with them is all i can say | 23:32 |
| twnqx | but i never used them in a case like this. | 23:32 |
| twnqx | well, if this blows up, i'll have an excuse to ditch the AVR, use an STM32 or other cortex m, and go all 3.3V | 23:33 |
| awygle | in case anybody was wondering, this is what i was thinking of before: https://observablehq.com/@nturley/netlistsvg-how-to-draw-a-better-schematic-than-graphviz | 23:56 |
| tpb | Title: Netlistsvg / Neil Turley / Observable (at observablehq.com) | 23:56 |
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