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| twnqx | hello. what does the message "ERROR: Multiple edge sensitive events found for this signal!" mean - edge sensitive events caused by said signal, or changing said signal? | 18:10 |
|---|---|---|
| awygle | i would assuming changing | 18:11 |
| awygle | since that's what would be an error | 18:11 |
| twnqx | me too, but there is exactly one in my code | 18:11 |
| twnqx | also, isn't it pretty common to have "always @(posedge a or posedge b)"? i am doing that all the time in xilinx ISE compiled stuff | 18:14 |
| twnqx | mostly in the form of "@(posedge reset or posedge clk)" | 18:14 |
| mwk | twnqx: your problem will be easier to diagnose if you show the relevant code | 18:15 |
| twnqx | https://gist.github.com/chrschmidt/c627cbb6c874f9468267aad4fbabc904 | 18:17 |
| tpb | Title: gist:c627cbb6c874f9468267aad4fbabc904 · GitHub (at gist.github.com) | 18:17 |
| mwk | and what are doing? this code seems to synth fine here | 18:18 |
| twnqx | would that move progval into the sensitivity list as it's purely combinatorical? | 18:18 |
| twnqx | well, it's only a part or the total code | 18:19 |
| twnqx | yosys -p "synth_ice40 -top top -blif ./build/ledpwm.blif" ledpwm.v would be the command | 18:19 |
| daveshah | FWIW, you should always be doing `always @*` rather than `always @(signal)` for combinational always | 18:20 |
| twnqx | mh let me clean out the reset signal, which the 384 doesn't have anyway | 18:20 |
| daveshah | otherwise you can end up with horrible sim/synth mismatches | 18:20 |
| daveshah | although I don't think that's the bug here | 18:20 |
| twnqx | that would be news to me, used @signal since... forever, with no mismatches with synplify/iverilog/ISE ever | 18:20 |
| twnqx | but ok | 18:21 |
| mwk | twnqx: the code you pasted works for me with synth_ice40 (after adding a blackbox for LEDMASK) | 18:21 |
| daveshah | If you use @(signals) then in simulation it is only updated when those signals change - but in synthesis that is not the case, it is treated like @* | 18:21 |
| mwk | are you using current yosys? | 18:21 |
| twnqx | 0.9 | 18:21 |
| twnqx | not git head | 18:21 |
| mwk | could you give me an actual reproducible complete command line + file that causes the error, then? | 18:22 |
| twnqx | soon, need to finish removing dead code | 18:22 |
| twnqx | since i learned that 384s can't generate a power-on reset :( | 18:23 |
| daveshah | None of the iCE40s can | 18:23 |
| twnqx | how do you set initial values in registers then, using initital? | 18:24 |
| daveshah | Oh, they all have a power on reset in that sense - you can use initial or `reg x = initval` | 18:25 |
| daveshah | There isn't an explicit power on reset signal though | 18:25 |
| daveshah | Strictly speaking, all registers are set to 0 at power on, but Yosys can fake 1-initialised registers by wrapping them in NOTs | 18:25 |
| twnqx | yeah, i'll rather assume 0-initialized. it's not that bad. | 18:29 |
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| twnqx | mwk: https://gist.github.com/chrschmidt/cb9107c47c0d47ab556ca0263c6283d8 - mind you, i wrote this a few weeks back and can't remember everything. it compiles fine with iverilog at least... | 18:33 |
| tpb | Title: gist:cb9107c47c0d47ab556ca0263c6283d8 · GitHub (at gist.github.com) | 18:33 |
| twnqx | still need to figure out SB_IO usage for this | 18:34 |
| twnqx | nah, something is definitely wrong here | 18:37 |
| twnqx | ... is verilog not case sensitive? | 18:38 |
| mwk | twnqx: can you please give me a testcase that reproduces the actual error that you're complaining about? | 18:38 |
| mwk | the code that you linked has a clear syntax error | 18:38 |
| * twnqx headdesks | 18:39 | |
| twnqx | sorry | 18:39 |
| mwk | and if I fix the syntax error, it synthesizes fine | 18:39 |
| twnqx | i was using a different copy in another user's directory, i was wondering why there was no error just now | 18:39 |
| twnqx | so i removed enough code to make it compile, just didn't notice | 18:41 |
| twnqx | is abc mandatory? | 18:41 |
| mwk | kinda | 18:41 |
| mwk | there are experimental abc-less flows | 18:41 |
| twnqx | so uh.. how do i make it find the abc binary? | 18:47 |
| twnqx | i just placed it in $HOME/bin | 18:47 |
| mwk | hmm | 18:48 |
| mwk | it should be called yosys-abc and be in the same directory as the yosys binary | 18:49 |
| twnqx | ah, so it's an issue with the gentoo ebuild :P ok, thank you, i'll look into building yosys the right way | 18:49 |
| twnqx | (who actually thinks that git pulling during compilation is a practical idea? compilation is absolutely sandboxes normally...) | 18:50 |
| ZirconiumX | twnqx: if you patch Yosys you can produce something that produces synthesis better than default but worse than ABC | 19:04 |
| ZirconiumX | Depends what you're targeting though | 19:04 |
| twnqx | i am just trying to figure out what i have to do to compile yosys in a fully sandboxed environment, that is, withoput network access | 19:07 |
| twnqx | and it seems that i have to just clone abc into the right place and check out the right revision | 19:07 |
| ZirconiumX | Yeah, basically. | 19:07 |
| somlo | twnqx: there's the ABCEXTERNAL environment variable you can use if you want to use your own ABC | 19:07 |
| twnqx | i noticed, but i'd still prefer to have the right revision | 19:08 |
| twnqx | easy anough to adobt the build script | 19:08 |
| somlo | the risc of course is that you've got an abc older than the minimum required by yosys -- so check the yosys makefile for the required (presumably "or later") abc commit ID | 19:08 |
| twnqx | adopt* | 19:08 |
| ZirconiumX | https://github.com/YosysHQ/yosys/pull/1691 if you're curious | 19:09 |
| tpb | Title: Use flowmap instead of gate2lut in noabc modes by ZirconiumX · Pull Request #1691 · YosysHQ/yosys · GitHub (at github.com) | 19:09 |
| ZirconiumX | FlowMap is interesting, if a bit impractical. | 19:19 |
| twnqx | ahahaha and there's a typo in 0.9 that will make preparing the exact revision impossible :P (it's lacking the last character of the git commit) | 19:25 |
| ZirconiumX | Uh, git will accept it just fine I think | 19:26 |
| twnqx | sure, but since it checks for that exact revision, the check will fail | 19:26 |
| ZirconiumX | Which is why we generally don't use the releases as such | 19:26 |
| twnqx | well, the Makefile is pretty adamant about that exact revision (unless setting ABCREV to default) | 19:27 |
| ZirconiumX | Yeah, because ABC has no release system at all | 19:28 |
| twnqx | :) and that's a working ebuild | 19:38 |
| twnqx | now for the next hurdle... nextpnr | 19:39 |
| ZirconiumX | There was a recent PR to make building ECP5 much easier | 19:45 |
| twnqx | i just have an ince40 384 | 19:46 |
| twnqx | ok, that's not drop-in compatible with arachne... | 19:48 |
| ZirconiumX | lp384? | 20:23 |
| az0re | How would everyone feel about a patch adding more precise source file location information to AST and RTLIL nodes? Specifically, AST node locations would be represented as {first_line, first_column, last_line, last_column}. I have used this in previous academic work and I think others might find it useful. The only problem is it touches rather a lot of code... | 20:33 |
| ZirconiumX | It would be a pretty wide-ranging change | 20:47 |
| ZirconiumX | You'd have to replace the parser, I think | 20:47 |
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| ZirconiumX | Maybe you can give Yosys good syntax error messages while you're at it :P | 20:47 |
| az0re | No, no need to replace the parser. Some modifications are necessary, but nothing really major. Mainly the YYLTYPE needs to be defined as a struct of four ints, and anything touching `linenum` needs to be changed to e.g. `location->first_line` or something better (like a precise file:column range). | 20:59 |
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| az0re | > Maybe you can give Yosys good syntax error messages while you're at it :P | 21:01 |
| az0re | Heh, well, I've always thought Yosys's syntax errors are great. But maybe my perception is jaded by my experience with syntax errors using ABC... ;) | 21:02 |
| ZirconiumX | Try using Rust for a few months | 21:02 |
| ZirconiumX | It becomes your benchmark of compiler error quality | 21:02 |
| az0re | Some day I will, for sure | 21:03 |
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| twnqx | success! sometimes you just need to step back and clear your mind by doing something completely different. | 22:01 |
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