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| az0re | what is the 'SEP' label applied to some issues in github? what does it mean? | 03:52 |
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| az0re | s/issues/PRs/ | 03:54 |
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| qu1j0t3 | interesting question, i haven't seen that. link? | 03:58 |
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| Xark | Apparently six flavors of "labels" on Yosys (e.g.). Not sure what SEP is though... https://github.com/YosysHQ/yosys/labels | 04:24 |
| tpb | Title: Labels · YosysHQ/yosys · GitHub (at github.com) | 04:24 |
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| lambda | re SEP: "somebody else's problem"? ;) though doesn't really make sense in the context of pull requests | 07:09 |
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| mwk | SEP stands for SymbioticEDA Process and is for prs that warrant a longer discussion in an all-hands meeting of yosys developers | 08:50 |
| mwk | (which is why the list of those should be getting shorter on thursdays) | 08:51 |
| az0re | I see, thanks | 08:58 |
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| thardin | hi, how complete is the xilinx 7 support? enough to use the transceivers, multipliers and external RAM? | 09:33 |
| sensille | i'm a bit perplexed: https://pastebin.com/VgFnziWB | 09:34 |
| tpb | Title: this assigns uart[channel]: always @(*) begin: uartmux integer i; - Pastebin.com (at pastebin.com) | 09:34 |
| sensille | this is with verilator. am i missing some verilog quirks? | 09:35 |
| lambda | thardin: I think all of those are still lacking in nextpnr-xilinx. I know DSP is not complete, haven't tested DRAM yet, but I think that has the highest chance of working out of those. | 09:37 |
| thardin | lambda: hm, ok | 09:40 |
| daveshah | litedram should work, but its a bit experimental | 09:40 |
| daveshah | multipliers work, other DSP functions don't necessarily | 09:40 |
| daveshah | no transceiver support at all atm | 09:40 |
| thardin | shame. but maybe one can rig a parallel interface with the I/Os | 09:41 |
| thardin | would it be possible to sponsor someone to take a crack at tramsceiver support? | 09:43 |
| daveshah | If you are talking a fully open source flow, the first step would be supporting them in prjxray | 09:46 |
| thardin | that's the RE stuff, right? | 09:46 |
| daveshah | Indeed | 09:47 |
| daveshah | mwk has also been doing some Xilinx RE but I don't know if she's looked at xc7 transceivers yet | 09:48 |
| mwk | not really, but they tend to go down quickly | 09:48 |
| mwk | it's just a bunch of attributes stored 1-1 into the bitstream | 09:49 |
| thardin | so I imagine | 09:49 |
| daveshah | If its anything like ecp5 the challenge is working out what those attributes actually do | 09:49 |
| daveshah | ie making a foss replacement to the Vivado wizard or whatever | 09:49 |
| thardin | seems the artix is a better deal than the kintex in terms of dsp/$ | 09:50 |
| mwk | *shrug* a valid way is just making a known-good template with vivado and reusing its attribute set | 09:50 |
| tnt | sensille: if those two behave differently that look slike a verilator bug to me. | 09:51 |
| tnt | (the only diff is the begin/end right ?) | 09:51 |
| thardin | mwk: right, should be possible to nail down in a reasonable amount of time. I poked at installing vivado a while back, maybe I'll give it a go again | 09:52 |
| mwk | also, note that in the meantime, yosys + Vivado P&R is a path that should be fully working | 09:53 |
| mwk | (if you can figure out how to instantiate the transceivers, which shouldn't be that hard) | 09:53 |
| sensille | tnt: right, begin/end changes behavior. i can't get it fully to work at all, so i'm suspecting i'm doing something wrong | 09:54 |
| thardin | hum-hum.. if I can do multi-drop LVDS then this might just be feasible | 09:55 |
| tnt | m-lvds is a thing but it's a bit != from lvds (termination etc ...) | 09:56 |
| thardin | of course | 09:56 |
| thardin | https://github.com/westonb/artix7-PCIe ooh | 10:00 |
| tpb | Title: GitHub - westonb/artix7-PCIe: artix-7 PCIe dev board (at github.com) | 10:00 |
| thardin | if it can DMA in/out of some GPUs then I'm all set | 10:01 |
| thardin | just got some replies from the HPC people, maybe I don't have to do this after all :) | 10:13 |
| sensille | it might have been related to the signal as being inout | 10:14 |
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| tnt | thardin: "Design has been built but prototypes were killed by JTAG ground loop due to user error." ... | 10:23 |
| thardin | tnt: a tale as old as electronics itself | 10:36 |
| thardin | I did some repair work on a pinball machine a while back where one of the problems was shitty grounding | 10:37 |
| thardin | grounded in a chain, so that the voltage drop at the end was high enough that solenoid transistors would spontaneously trigger | 10:38 |
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| sensille | any guesses what would be the best channel to ask about verilator? | 12:04 |
| ZirconiumX | ##openfpga seems like a sensible place to ask | 12:14 |
| ZirconiumX | I don't think it has a dedicated IRC channel | 12:14 |
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