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| strongsaxophone | is there any control option to force yosys accept a file without error ( syntax error, unexpected TOK_ID) | 12:30 |
|---|---|---|
| strongsaxophone | this error happend because of this part of code : | 12:31 |
| strongsaxophone | >------->-------for (int i = 0; i <= 3; i++) begin | 12:31 |
| strongsaxophone | >------->------->-------$display("register_file: register[%2d]: %2d",~ | 12:31 |
| strongsaxophone | >------->------->------->-------i, register[i]); | 12:31 |
| strongsaxophone | >------->-------end | 12:31 |
| daveshah | You could put the non synthesisable stuff in `ifndef SYNTHESIS | 12:39 |
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| strongsaxophone | it worked, thank you. | 12:57 |
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| peepsalot | ZirconiumX: a quick search for yosys+Quartus brings me to the vloghammer page, which has a bunch of stuff logged against quartus 17.0. are these part of what's blocking de10-nano progress? | 22:37 |
| peepsalot | is there any reason not to test later version such as Quartus 19.1? or its just not been tried yet for time reasons | 22:37 |
| ZirconiumX | peepsalot: vloghammer is a separate thing entirely | 22:38 |
| peepsalot | i tried to install various older versions but the installer is bugged in mint/ubuntu and couldn't even get them to work properly | 22:38 |
| ZirconiumX | peepsalot: so, Quartus has two kinds of file input types that we can produce | 22:39 |
| ZirconiumX | A "Verilog Quartus Mapping" which is fairly strict subset of Verilog | 22:40 |
| ZirconiumX | With terrible error messages because you're not supposed to get it wrong | 22:40 |
| peepsalot | mapping full verilog to this subset of verilog? kinda transpiling? | 22:42 |
| ZirconiumX | Well, the output is a netlist of Quartus cells | 22:43 |
| ZirconiumX | It's like Verilog but if everything is a module | 22:43 |
| peepsalot | ah ok | 22:44 |
| peepsalot | and the second type? | 22:47 |
| ZirconiumX | EDIF, which looks a lot like Lisp. Except it was very poorly specified and so compilers generally don't agree on what EDIF actually is | 22:47 |
| ZirconiumX | The current Yosys write_edif is targeted for Vivado | 22:48 |
| peepsalot | so you mentioned before that the netlist produced isn't compatible with Quartus for some reasons? | 22:51 |
| peepsalot | does quartus netlist format need to be RE'd or something? | 22:52 |
| ZirconiumX | peepsalot: It's very poorly documented, shall we say | 22:58 |
| ZirconiumX | peepsalot: https://github.com/YosysHQ/yosys/pull/1554#issuecomment-570623371 | 22:59 |
| tpb | Title: synth_intel_alm: replacement flow for ALM-based Intel FPGAs. by ZirconiumX · Pull Request #1554 · YosysHQ/yosys · GitHub (at github.com) | 22:59 |
| peepsalot | ZirconiumX: what is this "VQM Extractor and Language Functional Description, Version 2.0" mentioned in the comment? i couldn't find such a document | 23:37 |
| ZirconiumX | "This excerpt from that document found in the QUIP latest release" | 23:38 |
| ZirconiumX | Here probably referring to the Quartus University Interface Program | 23:39 |
| ZirconiumX | https://www.intel.com/content/www/us/en/programmable/support/support-resources/software/download/altera_design/quip.html maybe? | 23:40 |
| tpb | Title: Download the QUIP ToolkitDownload the QUIP Toolkit (at www.intel.com) | 23:40 |
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| peepsalot | yeah, i found the file in there, 15 yr old document is the latest?! | 23:50 |
| * GenTooMan just grins. | 23:51 | |
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