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peepsalot | hi. is it possible to use yosys with intel DE10-Nano boards? Cyclone V SE 5CSEBA6U23I7 | 00:07 |
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mwk | ZirconiumX: | 00:08 |
ZirconiumX | peepsalot: short answer: no. long answer: I'm working on it, and maybe soon we can. | 00:09 |
peepsalot | ok, i'm still absolute beginner to fpga, but more open source tools are very appealing to me :) | 00:10 |
peepsalot | ZirconiumX: do you own one? or is there anything I can help with testing? | 00:11 |
ZirconiumX | peepsalot: I'm at a stage where I can produce a netlist, but due to present Quartus incompatibilities (and bugs) you can't do anything with it | 00:12 |
ZirconiumX | I do indeed, as part of a MiSTer | 00:12 |
peepsalot | ah, nice, MiSTer is one of my main reasons for interest too | 00:12 |
ZirconiumX | Actually getting MiSTer to run on a purely-open toolchain is a long way off however | 00:13 |
peepsalot | ZirconiumX: do you work on any specific mister cores? | 00:13 |
ZirconiumX | I submitted a patch to Minimig | 00:13 |
ZirconiumX | But it got rejected because Sorgelig apparently can't read the Verilog LRM... | 00:14 |
peepsalot | :( | 00:15 |
ZirconiumX | Unfortunately even the most easily ported core - Minimig - is basically impractical to compile at present, because while the Amiga chipset is implemented in Verilog, the 68000 cores are all VHDL | 00:15 |
ZirconiumX | And Yosys has no native VHDL support | 00:16 |
ZirconiumX | There is an ongoing effort to use GHDL as a front-end module for VHDL, but that's beta-quality at best | 00:16 |
ZirconiumX | And requires an Ada toolchain that most people won't have by default | 00:17 |
peepsalot | i want to try to implement some vector display arcade stuff like battlezone etc. | 00:17 |
ZirconiumX | peepsalot: with all of that said, I would greatly appreciate whatever help you think you can offer. | 00:18 |
peepsalot | my dream goal is to interface with laser projector so I can put it on my ~200" display...a white wall in my house ;) | 00:19 |
ZirconiumX | That sounds wonderful | 00:20 |
peepsalot | its a little disappointing that the lead dev seems so hard to work with | 00:23 |
ZirconiumX | Yeah... | 00:23 |
peepsalot | but yeah as I said, i'm only absolute beginner to FPGA, so probably not much help to you. still trying to grasp the very basics of HDL etc. i've been a software programmer for many years though | 00:32 |
* N2TOH just got his Spartan 6 board the other day | 00:32 | |
ZirconiumX | peepsalot: much of what I'm working on is the software side of it all | 00:32 |
ZirconiumX | N2TOH: thank mwk for adding xc6s support to Yosys (using ISE as a backend) | 00:33 |
N2TOH | *nods* | 00:34 |
N2TOH | my JTAG adapter is sill in China so I need something | 00:34 |
N2TOH | my end use should be simple enough | 00:36 |
N2TOH | gonna use it as a memory manager for a 65C816 | 00:36 |
N2TOH | I went with this FPGA cause it has enough IO | 00:36 |
N2TOH | never mind it has enough logic to IMPLEMENT the CPU I'm interfacing too! | 00:37 |
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* N2TOH reads how to wire up an FTDI chip to this FPGA board | 02:26 | |
peepsalot | can place and route be accelerated by solving ON an FPGA? | 02:36 |
OK_b00m3r | there are some papers on that iirc | 02:39 |
N2TOH | where is a list of known good JTAG interfaces? | 02:40 |
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N2TOH | should getting Xilinx ISE be a tremendous pain to get running? | 05:03 |
N2TOH | https://imgur.com/gallery/rUQgfyb | 05:07 |
tpb | Title: Imgur: The magic of the Internet (at imgur.com) | 05:07 |
peepsalot | well, i don't know specifically about xilinx, but I'm pretty sure there's its been mandated that all embedded tools be as cumbersome as imaginable | 05:16 |
N2TOH | I installed it and had it running, now I can't recall how to start it | 05:17 |
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N2TOH | HOA=Horribly Organized Assholes | 05:50 |
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mwk | N2TOH: yes, ISE is a pain, that's normal | 09:12 |
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N2TOH | I seem to have forgotten how to get it started after installing and running it once | 09:29 |
N2TOH | that also seem normal when playing with ubuntu | 09:29 |
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