Thursday, 2020-01-23

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awygleCan I communicate to yosys/abc/nextpnr that the calculation I've described must complete within X cycles of a Y MHz clock, please optimize it for area?21:05
tntwithin X cycles ?  nextpnr doesn't have multi-cycle constraint in the first place.21:06
daveshahYeah, nextpnr doesn't support this yet21:07
awyglethat's more or less what i expected21:07
awyglethanks tho21:07
awyglei was thinking maybe abc's "retiming" stuff could be used for this somehow21:07
daveshahYou could probably give abc a delay constraint of X/Y21:07
sorearwhat tools *do* have that kind of multi-cycle constraint?21:07
daveshahBut abc's delay constraints don't tend to yield vast area improvements21:07
daveshahAt least some of the vendor onez21:08
tntawygle: well it's not the same thing as retiming.21:08
daveshah*ones21:08
awygleanother channel recommended trying vivado hls21:08
tntthat's _yet_ another different thing than multi-cycle constraints ...21:08
awygletbf, i didn't say "multi cycle constraints", you did21:09
tntretiming is moving pipeline register around to try and equalize the paths between FFs.21:09
soreardo you have throughput requirements?21:09
awygleyou can see the relation though, yes? i want to add or remove pipeline registers to try to minimize total area. that the one might apply to the other is not a crazy thought.21:10
tntmulti-cycle constraint is allowing the comb logic to take more time between FFs than the normal clock period because you guarantee externaly, somehow, that the input is going to be state for N cycles on you will only clock enable the output after N cycles.21:10
tntHLS will potentially generate completely different logic and data path and everything depending on a set of parameters.21:11
awyglesorear: kind of? i have a calculation, which must happen within (say) 16 clock cycles. after 16 clock cycles i should be able to launch the calculation again. that's all i really want.21:11
daveshahabc's retiming is pretty crap tbh21:11
daveshahThere was talk of doing retiming in Yosys itself but that seems to have stalled, there isn't even a timing framework yet afaics21:11
tntalso in fpga, pipeline registers can often be free since they're already after each lut wether you use them or not.21:12
daveshahYep21:13
daveshahI think doing post placement retiming in nextpnr could be interesting for larger devices21:13
daveshahParticularly once you get into Xilinx "3D" die crossing21:13
daveshahBut that's a digression21:13
awygleI'll play with the hls stuff, see how that goes. Thanks all.21:16
tntSo realistically area really won't change drastically. If you have 16 cycles the only thing that would change it a lot is if you can  do resource re-use / sharing without paying too much for the muxes needed for that, but no tool is going to do that for you, that's your job as the designer.21:16
awyglea tool absolutely should be able to tell me that, it's a completely deterministically knowable thing.21:17
tntFeel free to write it.21:19
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