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awygle | Can I communicate to yosys/abc/nextpnr that the calculation I've described must complete within X cycles of a Y MHz clock, please optimize it for area? | 21:05 |
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tnt | within X cycles ? nextpnr doesn't have multi-cycle constraint in the first place. | 21:06 |
daveshah | Yeah, nextpnr doesn't support this yet | 21:07 |
awygle | that's more or less what i expected | 21:07 |
awygle | thanks tho | 21:07 |
awygle | i was thinking maybe abc's "retiming" stuff could be used for this somehow | 21:07 |
daveshah | You could probably give abc a delay constraint of X/Y | 21:07 |
sorear | what tools *do* have that kind of multi-cycle constraint? | 21:07 |
daveshah | But abc's delay constraints don't tend to yield vast area improvements | 21:07 |
daveshah | At least some of the vendor onez | 21:08 |
tnt | awygle: well it's not the same thing as retiming. | 21:08 |
daveshah | *ones | 21:08 |
awygle | another channel recommended trying vivado hls | 21:08 |
tnt | that's _yet_ another different thing than multi-cycle constraints ... | 21:08 |
awygle | tbf, i didn't say "multi cycle constraints", you did | 21:09 |
tnt | retiming is moving pipeline register around to try and equalize the paths between FFs. | 21:09 |
sorear | do you have throughput requirements? | 21:09 |
awygle | you can see the relation though, yes? i want to add or remove pipeline registers to try to minimize total area. that the one might apply to the other is not a crazy thought. | 21:10 |
tnt | multi-cycle constraint is allowing the comb logic to take more time between FFs than the normal clock period because you guarantee externaly, somehow, that the input is going to be state for N cycles on you will only clock enable the output after N cycles. | 21:10 |
tnt | HLS will potentially generate completely different logic and data path and everything depending on a set of parameters. | 21:11 |
awygle | sorear: kind of? i have a calculation, which must happen within (say) 16 clock cycles. after 16 clock cycles i should be able to launch the calculation again. that's all i really want. | 21:11 |
daveshah | abc's retiming is pretty crap tbh | 21:11 |
daveshah | There was talk of doing retiming in Yosys itself but that seems to have stalled, there isn't even a timing framework yet afaics | 21:11 |
tnt | also in fpga, pipeline registers can often be free since they're already after each lut wether you use them or not. | 21:12 |
daveshah | Yep | 21:13 |
daveshah | I think doing post placement retiming in nextpnr could be interesting for larger devices | 21:13 |
daveshah | Particularly once you get into Xilinx "3D" die crossing | 21:13 |
daveshah | But that's a digression | 21:13 |
awygle | I'll play with the hls stuff, see how that goes. Thanks all. | 21:16 |
tnt | So realistically area really won't change drastically. If you have 16 cycles the only thing that would change it a lot is if you can do resource re-use / sharing without paying too much for the muxes needed for that, but no tool is going to do that for you, that's your job as the designer. | 21:16 |
awygle | a tool absolutely should be able to tell me that, it's a completely deterministically knowable thing. | 21:17 |
tnt | Feel free to write it. | 21:19 |
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