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| benzn1989 | Any experts on nextpnr here? Trying to manually place some things and don't really see how this is supposed to work given that the HEaP manually rips up everything on every iteration. | 03:14 |
|---|---|---|
| benzn1989 | Perhaps I can figure out how the SB_IOs are constrained | 03:28 |
| benzn1989 | (since they definitely aren't allowed to move around) | 03:28 |
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| benzn1989 | Aha, it rips up everything that's not the root of a carry chain | 04:14 |
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| awygle | that's odd. i ran the same build of yosys against the same verilog file with synth_ecp5 under windows (cygwin) and under linux and got different results. | 22:38 |
| daveshah | There are some known issues in that respect | 22:40 |
| daveshah | Related, iirc, to something like destructor ordering | 22:40 |
| awygle | i see | 22:41 |
| awygle | also, -abc9 does not work for synth_ecp5 under cygwin (fails to read the lut file). i don't know if that matters to anyone but me tho | 22:42 |
| daveshah | That's definitely worth filing an issue for | 22:50 |
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| awygle | i suppose i should also include "you have to delete -fPIC to compile under cygwin" as well then | 23:00 |
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| ZirconiumX | I think it's interesting to note how the primary driver of nextpnr performance is bigger target chips. | 23:03 |
| ZirconiumX | e.g. ECP5 resulted in HeAP placement because SA takes a good while | 23:03 |
| ZirconiumX | And now Xilinx targeting has router2 | 23:03 |
| daveshah | router2 is nothing to do with Xilinx being bigger fwiw | 23:04 |
| daveshah | It doesn't actually perform much better even on big ECP5 designs right now | 23:04 |
| ZirconiumX | Hmm, I got the impression of that from your Patreon post | 23:05 |
| daveshah | But on ECP5 sized Xilinx designs it copes much better because it handles the resultant congestion better | 23:05 |
| ZirconiumX | Ah, okay | 23:05 |
| daveshah | The hope was that it would scale better but the most pressing concern was dealing with the congestion from having fewer routing resources | 23:05 |
| ZirconiumX | I had a look at nextpnr-xilinx and noted there was an option for OpenMP acceleration in the CMakeLists | 23:05 |
| daveshah | There is in normal nextpnr too | 23:06 |
| daveshah | It speeds up the sparse matrix solving part of HeAP slightly | 23:06 |
| awygle | ZirconiumX and I were just talking about this out of band but is nextpnr likely to have an issue routing two independent designs in the same, uh, "project"? i.e. two sections of the chip being totally unconnected and on separate clock domains? | 23:06 |
| daveshah | Overheads mean it is only worth it for big designs | 23:06 |
| daveshah | awygle: unlikely I'd say | 23:06 |
| daveshah | Router definitely should care | 23:07 |
| daveshah | *shouldn't | 23:07 |
| ZirconiumX | I mean, one of the designs has a target Fmax of a few megahertz | 23:07 |
| daveshah | So long as each part has some external IO, placement shouldn't be a problem either | 23:07 |
| ZirconiumX | So it shouldn't have problems in meeting timing | 23:07 |
| daveshah | nextpnr should already optimise each clock domain somewhat separately anyway | 23:08 |
| awygle | lol: "Info: Max frequency for clock 'ap_clk': 192.57 MHz (PASS at 2.00 MHz)" | 23:09 |
| ZirconiumX | I feel like my chess move generator is going to be an excellent example of an overcongested design >.> | 23:11 |
| awygle | nextpnr is so fast ;_; it finished in less than a second, diamond can't even start that fast | 23:11 |
| ZirconiumX | I mean, it depends on the design, naturally | 23:12 |
| awygle | sure, but still | 23:12 |
| ZirconiumX | ...I still wish I could use Quartus on out of context designs... | 23:12 |
| awygle | is the packer fully deterministic? | 23:14 |
| daveshah | I think so | 23:14 |
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