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| Xiretza | just got to the point where my SoC successfully gets through ghdl and Yosys, but nextpnr-xilinx fails because I have too many global clocks. looking at them, there are 4 with cryptic names like '$auto$clkbufmap.cc:247:execute$237951' - any tips on tracing those back to their approximate context in the design? | 12:34 |
|---|---|---|
| daveshah | Find the BUFG in the netlist (perhaps do a write_ilang at the end as that should be more readable than the JSON) and have a look at the input name | 12:46 |
| mwk | Xiretza: try synth_xilinx -noclkbuf | 12:54 |
| mwk | this will disable the clkbufmap pass | 12:54 |
| daveshah | Then you will need to instantiate BUFGs manually as nextpnr-xilinx currently relies on Yosys to promote them | 12:56 |
| mwk | hmm right | 12:57 |
| daveshah | In this case I think '$auto$clkbufmap.cc:247:execute$237951' are usually clock buffer inputs | 12:59 |
| Xiretza | indeed | 12:59 |
| daveshah | somewhat confusingly the current hacky clock router in nextpnr-xilinx also lists these as global clocks because it uses a similar algorithm to route them | 12:59 |
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| ZirconiumX | So, here's a question: how does one create an asynchronous load when you only have a synchronous load input? | 17:56 |
| ZirconiumX | The Cyclone V LAB has 3 clock inputs, a synchronous-load line, a synchronous-clear line, and two asynchronous-clear lines | 18:02 |
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| daveshah | > So, here's a question: how does one create an asynchronous load when you only have a synchronous load input? | 18:17 |
| daveshah | I expect the same way you fake async set and reset on devices that only have one or the other | 18:18 |
| daveshah | more or less two FFs one with an async set and one with an async reset; and a latch and mux to select the last one asserted | 18:18 |
| sorear | isn't "latch" the same thing as "asynchronous load" and thereby begging the question | 18:19 |
| daveshah | Well, a latch is easy enough to make out of a LUT | 18:19 |
| daveshah | I'm guessing asynchronous load was FF + async load | 18:20 |
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| Xiretza | is there a pass in yosys that removes all $assert/$assume/$cover cells? VHDL doesn't have the same preprocessor mechanic as verilog, so turning off generation of verification blocks in the frontend isn't quite as straightforward. | 22:33 |
| daveshah | Xiretza: chformal -remove | 22:35 |
| Xiretza | daveshah: thanks, that's a useful command! | 22:36 |
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