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blackbit | pepijndevos: i _finally_ got the two Tang Nano boards I ordered back in november. did you find time to work on the yosys support? | 10:34 |
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ZirconiumX | blackbit: it got merged into Yosys a good while back | 10:35 |
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blackbit | oh wow | 10:36 |
blackbit | cool stuff | 10:36 |
blackbit | will take a look! | 10:36 |
blackbit | i actually have the rss feed of yosys commits subscribed, i must have overlooked that | 10:36 |
ZirconiumX | https://github.com/yosyshq/yosys/pulls?utf8=%E2%9C%93&q=is%3Apr+gowin | 10:37 |
tpb | Title: Pull Requests · YosysHQ/yosys · GitHub (at github.com) | 10:37 |
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ZirconiumX | blackbit: ^ | 10:41 |
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blackbit | nice | 12:07 |
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ZipCPU | I'd like to respond to my own tweet (and thread) https://twitter.com/zipcpu/status/1219386335632461825 by stating that the iCE40 doesn't support memory reads into a register with an initial value | 13:34 |
ZipCPU | That it's not the synthesizers fault. | 13:34 |
ZipCPU | I thought I might check here first, though, to double check | 13:34 |
daveshah | Yes, that's correct, iCE40 BRAM output registers are undefined at startup | 13:35 |
ZipCPU | ... and so the hardware itself has no way of supporting an initial statement | 13:35 |
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daveshah | Indeed | 13:35 |
ZipCPU | Also known as, "and this is why we can't have nice things" ... | 13:35 |
ZipCPU | ;) | 13:35 |
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whitequark | oof, this makes it even more important to support uninitialized registers in nmigen | 13:43 |
whitequark | since even some BRAMs require it... | 13:43 |
ZirconiumX | I think the CV MAC units power up with uninitialised accumulator registers, but I should go check | 13:54 |
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Xiretza | I can't seem to get yosys to synthesize asymmetric memories (e.g. one 32-bit write port, one 8-bit read port), neither synth_ecp5 nor synth_xilinx find a matching block RAM. am I doing something wrong or is that just how it is? | 20:03 |
Xiretza | oh, just found https://github.com/YosysHQ/yosys/issues/1134, sorry. | 20:04 |
tpb | Title: Issues · YosysHQ/yosys · GitHub (at github.com) | 20:04 |
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