Tuesday, 2020-01-21

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blackbitpepijndevos: i _finally_ got the two Tang Nano boards I ordered back in november. did you find time to work on the yosys support?10:34
ZirconiumXblackbit: it got merged into Yosys a good while back10:35
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blackbitoh wow10:36
blackbitcool stuff10:36
blackbitwill take a look!10:36
blackbiti actually have the rss feed of yosys commits subscribed, i must have overlooked that10:36
ZirconiumXhttps://github.com/yosyshq/yosys/pulls?utf8=%E2%9C%93&q=is%3Apr+gowin10:37
tpbTitle: Pull Requests · YosysHQ/yosys · GitHub (at github.com)10:37
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ZirconiumXblackbit: ^10:41
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blackbitnice12:07
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ZipCPUI'd like to respond to my own tweet (and thread) https://twitter.com/zipcpu/status/1219386335632461825 by stating that the iCE40 doesn't support memory reads into a register with an initial value13:34
ZipCPUThat it's not the synthesizers fault.13:34
ZipCPUI thought I might check here first, though, to double check13:34
daveshahYes, that's correct, iCE40 BRAM output registers are undefined at startup13:35
ZipCPU... and so the hardware itself has no way of supporting an initial statement13:35
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daveshahIndeed13:35
ZipCPUAlso known as, "and this is why we can't have nice things" ...13:35
ZipCPU;)13:35
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whitequarkoof, this makes it even more important to support uninitialized registers in nmigen13:43
whitequarksince even some BRAMs require it...13:43
ZirconiumXI think the CV MAC units power up with uninitialised accumulator registers, but I should go check13:54
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XiretzaI can't seem to get yosys to synthesize asymmetric memories (e.g. one 32-bit write port, one 8-bit read port), neither synth_ecp5 nor synth_xilinx find a matching block RAM. am I doing something wrong or is that just how it is?20:03
Xiretzaoh, just found https://github.com/YosysHQ/yosys/issues/1134, sorry.20:04
tpbTitle: Issues · YosysHQ/yosys · GitHub (at github.com)20:04
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