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| develonepi3 | mmicko From cmd line can set BUILD GUI OFF like -DARCH=ice40? | 14:22 |
|---|---|---|
| mmicko | sure -DBUILD_GUI=OFF | 14:23 |
| develonepi3 | mmicko I see -- Configuring architecture : ice40. | 14:29 |
| develonepi3 | then -- Configuring incomplete, errors occurred! | 14:29 |
| develonepi3 | mmicko this is what I used "-DARCH=ice40 -DBUILD_GUI=OFF ." | 14:30 |
| mmicko | if you do not have boost python add -DBUILD_PYTHON=OFF | 14:31 |
| develonepi3 | I do have boost1.71? | 14:33 |
| janrinze | ZipCPU: Your SPI SDcard simulator, is it okay for use in an emulator that uses byte read/write to a memory mapped SPI port? | 14:35 |
| ZipCPU | ? | 14:36 |
| ZipCPU | I'm not sure I follow | 14:36 |
| janrinze | ZipCPU: it looks sufficiently comprehensive in that it simulates an SDcard in SPI mode | 14:36 |
| ZipCPU | Yes, that's the purpose of it | 14:36 |
| janrinze | https://github.com/ZipCPU/sdspi/blob/master/bench/cpp/sdspisim.cpp | 14:36 |
| tpb | Title: sdspi/sdspisim.cpp at master · ZipCPU/sdspi · GitHub (at github.com) | 14:36 |
| ZipCPU | Okay, we are talking about the same simulator | 14:37 |
| ZipCPU | But ... what constitutes a "memory mapped SPI port"? | 14:37 |
| ZipCPU | Flash memory? | 14:37 |
| janrinze | I have an Acorn Atom emulator that uses a hardware SPI port (8bit) that is accessed at a memory address | 14:37 |
| ZipCPU | Okay, but ... that's not specific enough to answer the question | 14:38 |
| janrinze | so it is a write to that address and a read to see the result | 14:38 |
| ZipCPU | That doesn't sound similar to the SD card's SPI protocol. | 14:38 |
| ZipCPU | In the SD card protocol, you write commands such as read or write sector to the card | 14:38 |
| janrinze | the write triggers the transfer, the read is done after a sufficiently long delay | 14:39 |
| ZipCPU | You then read/write a sector of data | 14:39 |
| mmicko | develonepi3: try with this parameter, boost python is usually separate install since it is optional and it is not in default build, so check without python support | 14:39 |
| janrinze | The protocol is handled in software | 14:39 |
| ZipCPU | The SD Card SPI protocol also has a rather complicated start up procedure | 14:39 |
| janrinze | It already runs on the FPGA, now i'd like to use the software emulator with the same ROM | 14:40 |
| ZipCPU | Would the flash emulator be more appropriate? | 14:40 |
| ZipCPU | https://github.com/ZipCPU/qspiflash/blob/master/bench/cpp/flashsim.cpp ? | 14:40 |
| tpb | Title: qspiflash/flashsim.cpp at master · ZipCPU/qspiflash · GitHub (at github.com) | 14:40 |
| ZipCPU | That can handle reading and writing bytes, but again it's not a generic protocol--it's supporting a flash SPI protocol | 14:41 |
| ZipCPU | The flash requires specific commands to read and write from and to various addresses | 14:41 |
| janrinze | Let me explain, There is a ROM that implements a filing system and uses the SDcard SPI protocol to interface with the SDcard. | 14:41 |
| ZipCPU | Ahh ... okay, so you already know that it's the SD card SPI protocol? | 14:41 |
| janrinze | Yes. It already runs on my FPGA | 14:42 |
| janrinze | can read/write files on the SDcard. | 14:42 |
| ZipCPU | That sounds like it'd be worth trying | 14:42 |
| ZipCPU | Are you using Verilator? | 14:43 |
| janrinze | The emulator is written in C/C++ | 14:43 |
| ZipCPU | Oh? No Verilog? | 14:43 |
| janrinze | Nope. The FPGA design is in verilog though. | 14:44 |
| janrinze | But running the Verilator version would cause quite a bit of overhead. | 14:44 |
| ZipCPU | Okay ... so, this still sounds doable, but you might need some more patching to make it work | 14:44 |
| janrinze | Yeah, that's what i am looking at. | 14:45 |
| ZipCPU | The SDSPI emulator takes CSn, SCK, and MOSI in, and returns MISO as a result | 14:45 |
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| janrinze | I think if i can modify it a little to have a byte interface ( just skipping the SPI clocks and such) it might just work. | 14:46 |
| ZipCPU | I make no warranties or guarantees | 14:46 |
| ZipCPU | :D | 14:46 |
| janrinze | :D understood. | 14:46 |
| janrinze | bottom line is just to have the appropriate communication and responses, including the read and write to a block of memory that holds the SDcard image. | 14:47 |
| ZipCPU | Well ... it might be worth trying | 14:49 |
| janrinze | there are some ROMs that use bitbanging interfaces that might be more appropriate for more direct implementation of your source code. | 14:49 |
| janrinze | Can try both solutions. | 14:49 |
| janrinze | The SDcard image is a whopping 100MB :-) | 14:50 |
| ZipCPU | Wow | 14:50 |
| janrinze | holds 1024 floppy images :D | 14:50 |
| ZipCPU | Hmm ... not sure if I should be impressed or dismayed at that statistic | 14:50 |
| martin2250 | Hi everyone! I'm new here and I need some help getting my iCE40 boards working, anyone here who has some experience with the boot/configuration process or who can point me in the right direction? | 14:51 |
| ZipCPU | It's like saying I can run 50k slide rules all at once to do calculations ... | 14:51 |
| ZipCPU | martin2250: Were you the one posting to reddit the other day? | 14:51 |
| janrinze | haha.. 1980's system so we're actually talking about a 6502 system with SDcard :D | 14:51 |
| martin2250 | yes, that was me | 14:51 |
| ZipCPU | martin2250: Welcome to the channel | 14:51 |
| janrinze | hi martin2250 | 14:52 |
| janrinze | martin2250: which iCE40 board? | 14:52 |
| ZipCPU | I don't think I've tried configuring any of my iCE40s from flash | 14:52 |
| janrinze | i have. | 14:52 |
| janrinze | martin2250: using the yosys/nextpnr/icestorm tools? | 14:53 |
| ZipCPU | The tinyfpga code should be a decent example of what needsd to happen | 14:53 |
| martin2250 | I've documented the problems on reddit: https://www.reddit.com/r/FPGA/comments/edgb7y/ice40_wont_finish_configuration/ | 14:53 |
| tpb | Title: iCE40 won't finish configuration : FPGA (at www.reddit.com) | 14:53 |
| ZipCPU | Sounds like you are missing a sync word of some type | 14:55 |
| martin2250 | it's a basic breakout board for the LP1K-CM36. I've had to connect some pins together to get to inner pins but according to the documentation that should be fine | 14:55 |
| janrinze | martin2250: mosi miso not swapped? (there were some people with that issue on boards.) | 14:55 |
| martin2250 | @ZipCPU did you read the post before the edit? I've tried to do slave configuration and it seems to accept the bitstream, just not actually start up | 14:56 |
| ZipCPU | Yeah ... I read it ... it doesn't make sense though, so I'm not sure how to comment on that | 14:56 |
| ZipCPU | I'd be curious to know your answer to janrinze's question | 14:57 |
| martin2250 | janrinze I've looked at all traces on the scope and to my eye, the communication seems fine | 14:57 |
| ZipCPU | Can you configure the FPGA at all? | 14:57 |
| ZipCPU | If you could configure the FPGA at all, you might then be able to determine if the flash works according to spec and pinouts | 14:58 |
| janrinze | martin2250: I has some trouble with flash not waking up but you see the correct data stream so that's not the cause. | 14:58 |
| ZipCPU | Correct data streaming into ... the correct pin? | 14:59 |
| martin2250 | I didn't get it to work so far. As described in the edit only indication that the bitstream is accepted by the FPGA is the fact that the pins take the correct state | 14:59 |
| martin2250 | yes, I've tried swapping pins and it resulted in a short (with CC enabled on the lab supply of course) | 15:00 |
| janrinze | the pins , meaning the bitstream is loaded and the device is setting up I/O pins to the correct states? | 15:00 |
| martin2250 | also it reacts differently when the flash is unprogrammed (it tries 6 times to load an image and then gives up) | 15:00 |
| janrinze | have you been able to verify your design on a differen HX1K board? | 15:01 |
| martin2250 | janrinze when I assign a pin to a state in verilog and use slave configuration, the correct pin gets pulled to the correct level. the pin just doesn't go out of high-impedance mode | 15:01 |
| ZipCPU | Then how do you know it gets pulled to the correct level? That doesn't make sense ... ? | 15:02 |
| janrinze | indeed. | 15:02 |
| develonepi3 | mmicko I used this, "-DARCH=ice40 -DBUILD_GUI=OFF -DBUILD_PYTHON=OFF .". I get -- Configuring architecture : ice40 then -- Configuring incomplete, errors occurred! The same without "-DBUILD_PYTHON=OFF". | 15:02 |
| martin2250 | according to the datasheets, the bitstream takes effect immediately as it is loaded. when the configuration is finished, the pins go to low-z mode. so it seems the bits end up at the right place in SRAM | 15:02 |
| janrinze | martin2250: have you tried something like a blinky to see if you can toggle an output at a certain frequency? | 15:04 |
| martin2250 | >Then how do you know it gets pulled to the correct level? I've connected a LED +resistor to the pin. so if the pin gets pulled up by a weak pullup, I can see the forward voltage on the scope. when I configure the pin as output/low, the voltage at the pin goes to zero | 15:04 |
| martin2250 | same with all pins I've tried | 15:04 |
| martin2250 | this doesn't happen if the pin is not configured or configured as an input | 15:05 |
| ZipCPU | Okay ... might it be a CRC issue with the flash image? | 15:05 |
| janrinze | martin2250: do you have the I/O bank voltages correctly connected? | 15:05 |
| ZipCPU | If it gets almost all of it, but doesn't finish properly, missing a CRC sounds like a possibility | 15:05 |
| martin2250 | janrinze yeah, apart from the 'assign pin' tests, that's what I've tried to get working | 15:06 |
| ZipCPU | janrinze seems to have the better questions though ... | 15:06 |
| martin2250 | a crc issue could be possible, it would fit the behavior, as the CRC is at the end of the file... that said I've used both icestorm and the official tools and both show the same behavior | 15:07 |
| martin2250 | IO and core voltages are fine. I've soldered two boards so I don't think it's a soldering mistake | 15:08 |
| martin2250 | does the iCE40 accept bitstreams that don't have the crc 'command' before the wakeup? maybe that's worth a try | 15:09 |
| whitequark | it seems strange that the pin output buffer gets *weakly* enabled | 15:09 |
| martin2250 | maybe it's just that the pullup resistor (which is active on an unconfigured device) gets disabled by the bitstream | 15:10 |
| ZipCPU | Wouldn't blinky flush that out? | 15:11 |
| daveshah | It sounds to me like pullups are being configured by the bitstream, but because configuration doesn't finish the global output enable isn't asserted | 15:12 |
| martin2250 | ZipCPU yes, that's (probably) why I see the voltage on the pin change when I upload blinky | 15:12 |
| daveshah | so the output drivers don't come on and the design doesn't do anything (internal write enable would be deasserted and FF reset asserted too) | 15:13 |
| martin2250 | nextpnr/icestorm and the official tools leave the pullup active for unused pins, so that's why it is different when I change the pin in the bitstream | 15:13 |
| martin2250 | daveshah yes, that describes the behavior pretty much perfectly | 15:14 |
| daveshah | That means either a CRC failures as discussed or a missing wakeup command | 15:14 |
| daveshah | Oh, do you have some clock cycles after the bitstream | 15:15 |
| martin2250 | the wakeup command is there (checked the bits on the scope). unless it somehow misses a bit and throws off alignment, it should work | 15:15 |
| martin2250 | yeah, I've even modified iceprog to conform better to the diagrams from the app note | 15:15 |
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| martin2250 | I'm using a FT2232 for sending the configuration. the edges look good | 15:16 |
| martin2250 | also tried the official lattice programmer at work (at least for flashing the flash chip, not for slave configuration) | 15:17 |
| daveshah | You could try reducing the clock frequency | 15:18 |
| daveshah | CDONE has a pullup? | 15:19 |
| martin2250 | not sure if it will make a difference... both iCE40 and FTDI are rated for much higher speeds. I'll give it a try, give me a minute | 15:19 |
| martin2250 | no, CDONE is connected to ground, as I had to make room for a via | 15:20 |
| janrinze | :D | 15:20 |
| martin2250 | all the documentation states that CDONE is output only, is this a problem? | 15:20 |
| tnt | cdone needs to be high | 15:20 |
| martin2250 | oh damn it | 15:21 |
| tnt | yea, the fpga will never finish config if cdone isn't pulled high. | 15:21 |
| tnt | I got bit by that ... I had a pull up on it and driving a transistor to light up a led ... but it then wouldn't rise above the 0.6v of the base-collector voltage and that prevented the ice40 from finishing config. | 15:22 |
| martin2250 | thanks, that should really be much more prominent in the documentation... | 15:22 |
| martin2250 | I'll try to scrape the pad off, maybe I can yet save the six boards I ordered... hopefully the FPGA survives the hot air gun treatment | 15:23 |
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| tnt | yeah, the doc and hw checklist tells you you need a pull-up but never _why_ and that despite being an output, it need to rise high for the fpga to actually finish config. | 15:27 |
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| martin2250 | does it have an internal pull up? | 15:28 |
| tnt | yes | 15:29 |
| martin2250 | (just checked, it does) | 15:29 |
| martin2250 | thanks | 15:29 |
| tnt | they do recommend an external one, so I'd add one for 'safety' on any future design, but at least this time you might be able to get the rework working by just dicsonnecting the ball. | 15:30 |
| tnt | maybe you can drill the via out from the other side ? | 15:30 |
| martin2250 | if I had enough room to route out the CDONE ball, I wouldn't have had to connect it to GND :P | 15:31 |
| martin2250 | the via connects all ground pins of that package, so that won't work | 15:31 |
| martin2250 | I'll head off to my workbench, back in a few minutes with good news hopefully. thanks for the help everybody and happy holidays! | 15:34 |
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| martin2250 | Hi again! Slave configuration works now, seems though as if the SPI_SO ball got disconnected, so I'll probably need a few more tries. reballing a BGA is harder than I thought, somehow the solder won't ball up on the chip | 16:44 |
| martin2250 | thanks again for your help! | 16:44 |
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