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| tux3 | My LUT usage goes up 600% if I move my AXI clk from the interface declaration to the modport... that doesn't seem right | 02:54 |
|---|---|---|
| ZipCPU | Evenin tux3 | 02:54 |
| tux3 | Hello! | 02:54 |
| ZipCPU | I'm not sure I follow your question ... can you share the two options you are coding? | 02:54 |
| ZipCPU | Is Yosys now supporting interfaces? | 02:56 |
| tux3 | Sortof, kinda! | 02:56 |
| tux3 | I get warnings that every wire of the interface is undefined in every module, but it synthetizes just fine | 02:57 |
| tux3 | That's a different story though =] | 02:57 |
| tux3 | Essentially, I have this AXI4 Lite bus in my toy softcore. It was declared as "interface axi(input aclk, input aresetn);" | 02:57 |
| ZipCPU | Did it build into something useful? | 02:57 |
| tux3 | Normally, yes. The module support seems to be hanging on by a thread, but as far as I can tell if all the stars align it works | 02:58 |
| tux3 | s/module/interface/ | 02:58 |
| tux3 | But actually, I'd like to reset that bus from one of the modports deep into the hierarchy, instead of where it's declared in the top module. Right? So I moved the aclk and aresetn in the master modport. | 02:58 |
| tux3 | After reducing the code a little, if I move the "assign bus.clk=clk" between my top module or a submodule, it goes from using 130 LUTs to 830 | 03:00 |
| ZipCPU | Yeah ... that sounds like something's not working | 03:01 |
| ZipCPU | You aren't supposed to be able to assign to something in a submodule, such as assign bus.clk=clk | 03:01 |
| ZipCPU | It's supposed to go the other way, busclk = bus.clk | 03:02 |
| ZipCPU | But that's with dot notation into submodules, not interfaces | 03:02 |
| ZipCPU | My point is simply that ... I don't think the standard supports it, and above that I'm not sure Yosys even fully supports the SV standard that defines those functions | 03:03 |
| tux3 | Hhhm not sure I understand. (Apologies if I'm a little slow, it's pretty late in my timezone!) | 03:03 |
| ZipCPU | Yeah ... getting late here | 03:03 |
| ZipCPU | The "dot" notation is supposed to only be used for unsynthesizable constructs--simulation test benches, formal properties, etc | 03:03 |
| tux3 | What I meant is I'm writing to my bus from the master side, through the master modport. The other side reads through its modport. I declare the appropriate signals as input/output and it all works — as long as there's no clk | 03:04 |
| ZipCPU | That doesn't sound like it works then | 03:04 |
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| tux3 | I was convinced modports were synthetizable, though I can understand SV features are pretty hit and miss in general... | 03:04 |
| ZipCPU | No clock? What is it building that doesn't have a clock, and how do you even know its building the right thing? | 03:04 |
| tux3 | So. The clk comes from the declaration in the top module "axi4lite sys_bus(.aclk(clk), .aresetn(!rst));" | 03:05 |
| tux3 | And then, I pass for example "sys_bus.master" to a submodule | 03:05 |
| tux3 | And the read side to another module | 03:05 |
| tux3 | Then they can talk to each other through their modports | 03:05 |
| ZipCPU | Ah, okay ... go on | 03:05 |
| tux3 | Now, I tried moving aclk/aresetn to the master modport, because it turns out I'd like the master to be in control or the reset. | 03:06 |
| tux3 | That blew up when I moved the clk. | 03:06 |
| tux3 | Maybe I should stick to boring old Verilog 2005 features, I guess I am asking for trouble =] | 03:07 |
| ZipCPU | Have you tried using the yosys "show" command on a simple design as a way of seeing what yosys is up to with the design you've given it? | 03:07 |
| tux3 | Nope. Not sure I'd be able to interpret the results to be entirely honest. I glanced at the routed results in the GUI, it looks like the read side of my bus is completely failing to meet timing and routed really poorly, but I don't really understand what's going on | 03:08 |
| tux3 | (This is probably the point where I should admit that I'm a software person and I have very little clue what I'm doing!) | 03:08 |
| ZipCPU | See ... that's me when I chat with clifford, "I don't know what's going on. Clifford then says, "Let's take a look" and the first thing he does is simplify the design, then he uses the "show" command to visualize it | 03:09 |
| ZipCPU | I've been surprised more than once at his ability to simplify a concept down to 5-10 lines of Verilog | 03:09 |
| ZipCPU | The graph then tends to make a lot of sense as we examine what's going on | 03:10 |
| tux3 | That sounds like a good plan. I wonder if there's something like creduce for verilog. | 03:11 |
| tux3 | I'll see if I can boil it down to a few lines tomorrow. Thanks for the help | 03:12 |
| ZipCPU | ;) | 03:14 |
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| ZipCPU | tux3: Out of curiosity ... what hardware are you using, and why are you using AXI at all? | 03:27 |
| tux3 | I only have a tinyfpga BX right now, but I'm trying to pretend verilog is a portable language and retargetting my code to Xiling series 7 down the line will go Just Fine | 03:29 |
| ZipCPU | I just ask because AXI is a rather heavy-weight protocol | 03:30 |
| ZipCPU | On a TinyFPGA, you're probably going to want to make every LUT count | 03:30 |
| ZipCPU | There are ... cheaper protocols than AXI | 03:30 |
| ZipCPU | (faster ones too) | 03:30 |
| tux3 | Well, it's AXI4-Lite and I'm implementing the bare minimum, but I'm actually trying really hard to exhaust the resources of my BX so I have an excuse to buy something bigger =] | 03:31 |
| tux3 | I really just need a vaguely standard 64bit interface. Wishbone looked like a good alternative. Is there something else I could have used? | 03:32 |
| ZipCPU | A 64-bit interface? AXI4-Lite is restricted to 32-bits only | 03:35 |
| ZipCPU | I'm personally very biased towards Wishbone (b4, pipelined), and I use it in everything I do | 03:36 |
| ZipCPU | It's cheaper, and tends to be faster than AXI | 03:36 |
| ZipCPU | Are you building a slave or a master? | 03:36 |
| ZipCPU | Are you building a single AXI4-Lite component, or a system containing many? | 03:36 |
| tux3 | Both | 03:37 |
| tux3 | Right now I really just have a quad-spi flash reader on the reader side (so not exactly taking full advantage of the 64bit bandwidth!) | 03:38 |
| tux3 | And the master is my ifetch | 03:38 |
| tux3 | If I ever get to using a board with some kind of DDR, the plan is to plug that on the other side of the bus and not have to change any part of my core | 03:39 |
| tux3 | I was going to go with axi4-lite for everything memory since that's the one I studied first and I don't really know any better, but I'm very open to suggestions =] ! | 03:40 |
| tux3 | Does the wishbone handshake roughly look like axi or is it something completely different? | 03:40 |
| ZipCPU | It's simpler | 03:40 |
| ZipCPU | The Valid/Ready request handshake is roughly the same when making a request, but there's only one request channel--not three | 03:41 |
| ZipCPU | There's also no stalling on the acknowledgment channel, and the write data doesn't need to be synchronized with the write address | 03:41 |
| ZipCPU | So, in AXI, you'd do ... if (AxVALID & AxREADY). In WB, this becomes if (i_wb_stb && !o_wb_stall) | 03:42 |
| ZipCPU | In AXI, you have to very carefully synchronize the AW* channel with the W* channel. In WB, if i_wb_stb && i_wb_we, it's a write request | 03:43 |
| ZipCPU | The write data is in i_wb_data, and the byte select lines in i_wb_sel | 03:43 |
| ZipCPU | The addresses are similar, save that AXI's addresses are octet addressed (w/ useless LSBs) whereas WB's are word addressed | 03:43 |
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| tux3 | Word addresses as in bus width? | 03:44 |
| tux3 | (No unaligned reads?) | 03:44 |
| ZipCPU | No unaligned reads. Everything is the width of the bus | 03:44 |
| tux3 | Hhm. That's a tradeoff, I can see how it'd make the slave side a lot simpler, but it might push some complexity into the master side | 03:45 |
| ZipCPU | Such as ... ? | 03:45 |
| ZipCPU | As far as I can tell, it just removes complexity | 03:45 |
| ZipCPU | For example, AXI slaves have to worry about setting AxREADY low when xREADY and xVALID have been high for more backpressure than the slave can handle | 03:47 |
| ZipCPU | However, in many Xilinx configurations, Xilinx guarantees that the xREADY lines are always high | 03:47 |
| ZipCPU | So that's a lot of excess slave logic you need to have that you aren't using | 03:48 |
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| tux3 | Yeah, it's a bit of a pain, I'll grant you that! | 03:48 |
| ZipCPU | Of course, if you change the Xilinx IP config, all of this changes | 03:48 |
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| tux3 | However I do like that axi can expose the full capabilities of my slave side without having to emulate it right on the critical path in my core. Even though, to be fair, things like misaligned reads are pretty rare in practice | 03:50 |
| ZipCPU | What full capabilities does AXI expose? | 03:50 |
| tux3 | Well, for example I was gawking at sifive's core designer recently | 03:50 |
| ZipCPU | Go on | 03:51 |
| tux3 | (Not that I have any ambition of ever getting anywhere near what they're doing, of course) | 03:51 |
| tux3 | They can happily swap out their bus data width between 32/64/128 AXI, and I don't think they need a whole lot of additional logic on the master side because of how flexible the bus is | 03:51 |
| tux3 | AXI allows some pretty crazy requests | 03:52 |
| ZipCPU | I'll admit, AXI makes adjusting bus width easier, but that capability is lost in AXI-lite once you drop the AxSIZE field | 03:52 |
| tux3 | That's fair | 03:53 |
| tux3 | You probably know more about this than I do, too =] | 03:53 |
| sorear | they’re not doing that in Verilog | 03:53 |
| ZipCPU | We should continue this discussion later. I'm struggling to keep my eyes open ;) | 03:53 |
| tux3 | Yeah | 03:53 |
| ZipCPU | sorear: How are they then doing it? In VHDL? ;) | 03:54 |
| sorear | Probably https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tilelink/ToAXI4.scala | 03:54 |
| tpb | Title: rocket-chip/ToAXI4.scala at master · chipsalliance/rocket-chip · GitHub (at github.com) | 03:54 |
| ZipCPU | Chisel? or Scala? Okay, I'll believe that. SiFive tends to use TileLink over AXI too. That's another discussion to have on another day | 03:55 |
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| develonepi3 | Hello all Does nextpnr depend on arachne-pnr chipdb*.bin files? | 15:24 |
| tnt | it needs the chip db from icestorm. Doesn't need anything from arachne. | 15:26 |
| tnt | (so the icebox/chipdb-*.txt) | 15:27 |
| develonepi3 | tnt When was chipdb-u4k added? | 15:28 |
| develonepi3 | tnt What program creates chipdb-*.bin files? | 15:29 |
| tnt | which ones ... both nextpnr and arachne have chipdb-* files and they're different ... | 15:30 |
| tnt | each set are created by helpers scripts in the compilation phase of each project. | 15:30 |
| tnt | (from the icebox text chipdb) | 15:31 |
| tnt | Not sure when the u4k support was added ... last summer or so ... | 15:31 |
| tnt | you'd have to check the commit logs | 15:31 |
| develonepi3 | tnt I have both arachne-pnr & nextpnr installed. Only see bin files /usr/local/share/arachne-pnr. | 15:32 |
| tnt | nextpnr doesn't install the .bin file by default. Instead they are "baked-in" the binary directly. | 15:33 |
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| develonepi3 | tnt In your version of nextpnr, is --package required? I am testing the latest ver of nextpnr on a rpi4-64 bit. | 15:41 |
| tnt | yes | 15:42 |
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| develonepi3 | Hello all I just pushed, to "https://github.com/develone/meta-yosys-tools/blob/master/doc-recipes/milestone.txt" and slides on a video "Containers in the embedded world" by Jeremy Rosen at youtube "https://www.youtube.com/watch?v=0S2Qow1IcQA", which might be useful for cross compiling with docker. It appears that mmicko is using docker for his cross commpiling. | 22:41 |
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