| *** tpb has joined #yosys | 00:00 | |
| *** emeb has quit IRC | 00:04 | |
| ZipCPU | piegames1: Welcome to the channel! | 01:21 |
|---|---|---|
| ZipCPU | Let me take a peek at that line ... | 01:22 |
| ZipCPU | Ahh, yes ... the reset within the faxil_slave works off of a *synchronous* reset | 01:23 |
| ZipCPU | As a result, if the reset is asserted on a given cycle, the VALID must be low on the *following* cycle | 01:23 |
| ZipCPU | As for asynchronous resets, anything asynchronous requires a synchronizer at the end of it. That means that a single clock cycle asynchronous reset isn't going to happen | 01:24 |
| ZipCPU | piegames1: Another thing to remember, according to spec you cannot have a combinational path between AXI inputs and outputs. That means everything must be registered. Registering the xVALID signals requires that it takes a clock to respond to a reset. | 01:51 |
| *** meawoppl has quit IRC | 02:00 | |
| *** d0nker5 has quit IRC | 02:17 | |
| *** d0nker5 has joined #yosys | 02:40 | |
| *** _whitelogger has quit IRC | 04:01 | |
| *** _whitelogger has joined #yosys | 04:03 | |
| *** s_frit has quit IRC | 04:10 | |
| *** s_frit has joined #yosys | 04:10 | |
| *** attie has joined #yosys | 04:29 | |
| *** attie has quit IRC | 04:34 | |
| *** _whitelogger has quit IRC | 04:58 | |
| *** _whitelogger has joined #yosys | 05:00 | |
| *** rohitksingh has joined #yosys | 05:07 | |
| *** rohitksingh has quit IRC | 05:59 | |
| *** Cerpin has quit IRC | 06:10 | |
| *** emeb_mac has quit IRC | 07:00 | |
| *** tmichalak has joined #yosys | 08:02 | |
| *** m4ssi has joined #yosys | 08:24 | |
| *** pie_ has quit IRC | 09:00 | |
| *** attie has joined #yosys | 09:18 | |
| *** dys has joined #yosys | 09:21 | |
| *** pie_ has joined #yosys | 09:40 | |
| *** fsasm has joined #yosys | 10:10 | |
| piegames1 | zipcpu, thanks and thanks. With the rule about "no combinatorial paths" I did not think of the reset as "input", but it kind of makes sense | 10:51 |
| *** pie_ has quit IRC | 11:28 | |
| *** pie_ has joined #yosys | 11:49 | |
| *** gmc has quit IRC | 12:08 | |
| *** finnb has joined #yosys | 13:09 | |
| finnb | Is there a place to talk about open source firmware in general? | 13:09 |
| whitequark | what kind of firmware? | 13:10 |
| finnb | FPGA firmware | 13:10 |
| finnb | any kind | 13:10 |
| whitequark | ##openfpga maybe | 13:10 |
| finnb | Thanks :) | 13:10 |
| *** lukego has quit IRC | 13:19 | |
| *** citypw has joined #yosys | 13:55 | |
| *** Jybz has joined #yosys | 14:29 | |
| *** pie_ has quit IRC | 14:56 | |
| *** emeb has joined #yosys | 15:14 | |
| *** fsasm has quit IRC | 15:25 | |
| *** citypw has quit IRC | 15:59 | |
| *** alexhw has quit IRC | 16:00 | |
| *** jakobwenzel has quit IRC | 16:05 | |
| *** alexhw has joined #yosys | 16:12 | |
| *** dys has quit IRC | 16:54 | |
| *** emeb has quit IRC | 17:55 | |
| *** m4ssi has quit IRC | 17:59 | |
| *** X-Scale has quit IRC | 18:31 | |
| *** X-Scale has joined #yosys | 18:36 | |
| *** rvense has quit IRC | 19:07 | |
| *** attie has quit IRC | 19:42 | |
| *** voxadam_ has quit IRC | 20:25 | |
| *** pie_ has joined #yosys | 20:38 | |
| *** rohitksingh has joined #yosys | 22:16 | |
| *** rohitksingh has quit IRC | 22:36 | |
| *** Jybz has quit IRC | 22:58 | |
| *** philtor has joined #yosys | 23:07 | |
| *** awordnot has quit IRC | 23:49 | |
| *** awordnot has joined #yosys | 23:50 | |
| *** emeb_mac has joined #yosys | 23:53 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!