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| mkurc | ZirconiumX: The solution that you suggested 'assign reset_val = (input_reset === 1'b0) ? 1'b0 : 1'b1' is not suitable for me. If I write such a statement in the techmap then it makes Yosys infer $mux cell. | 09:11 |
|---|---|---|
| mkurc | ZirconiumX: I need a way to determine whether a signal is unconnected inside a generate statement. The condition has to be constant during synthesis. | 09:12 |
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| ZirconiumX | mkurc: But as far as I can tell, Yosys can't do that at present, presumably because nobody thought you'd need to check for a port being disconnected. | 10:28 |
| whitequark | I think there is | 10:29 |
| whitequark | _TECHMAP_CONST{MSK,VAL}_ and _TECHMAP_CONNMAP_<PORT>_ can do this, no? | 10:29 |
| whitequark | of course, it's yosys-specific | 10:29 |
| ZirconiumX | We tried that | 10:29 |
| whitequark | ah | 10:30 |
| ZirconiumX | Actually, not CONNMAP. | 10:30 |
| ZirconiumX | Maybe worth trying that, mkurc | 10:30 |
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| daveshah | Verilog does support default port values (eg input wire rst = 1'b1) | 10:47 |
| daveshah | But I don't know if this works with techmap | 10:47 |
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| develonepi3 | mmicko Have you used Yocto? I have a Ubuntu system builds rpi4 which creates deb packages and rpi4-64 which creates rpm package. This appears to be a pretty good feature. Now if you I can just get nextpnr, yosys, and arachne-pnr to build. Yosys compiles but is getting a QA error Unable to recognise the format on yosys. Nextpnr I need to learn how to execute cmake -DARCH=ice40 . in a recipe. Makefiles just use oe_runmake. | 17:23 |
| develonepi3 | mmicko I now have icestorm_0.1+git0+041c075e4a-r0_armhf.deb or icestorm-0.1+git0+041c075e4a-r0.aarch64.rpm | 17:26 |
| develonepi3 | mmicko arachne-pnr I need to fix the use of sum which is in the Makefile. The sum which is in coreutils & busybox. | 17:30 |
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| meawoppl | heyo heyo | 19:22 |
| meawoppl | I have another small issue to report | 19:22 |
| meawoppl | *two small issues | 19:24 |
| meawoppl | I think using yosys as a total n00b to verilog has help me turn up the weird | 19:24 |
| meawoppl | bug #1: | 19:25 |
| meawoppl | bus assignment is ignored in weird ways: | 19:25 |
| meawoppl | `thing[7:0] <= otherThing[7:0];` | 19:25 |
| meawoppl | bug #2: | 19:26 |
| meawoppl | my IDE automatically adds: | 19:26 |
| meawoppl | `endmodule : ModuleName` which yosys seems to dislike... | 19:27 |
| meawoppl | vs. just `endmodule` | 19:27 |
| daveshah | Not sure about #2, I'd have to check the standard. Can you explain #1 better? | 19:32 |
| meawoppl | yeah, there are a bunch of permutations that seem to be quietly ignored: | 19:33 |
| meawoppl | so I think the vaslid way to do this is w/o the array notation: | 19:33 |
| meawoppl | `thing <= otherThing[7:0];` Which seems to work as expected | 19:34 |
| meawoppl | `thing <= otherThing[0:7];` is ignored (no bus endian swap?) | 19:35 |
| meawoppl | I am not sure which are/are not legal | 19:35 |
| * ZirconiumX is very glad they're not a language lawyer who has to deal with these kinds of questions | 19:36 | |
| daveshah | I don't think that does a bus endian swap | 19:36 |
| meawoppl | I think it isn't valid honestly, but it does get treated somehow strangly under the hood vs. a raised syntax exception or similar | 19:37 |
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