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| develonepi3 | mmicko ZipCPU recommended that I ask you. I was able to build icestorm 8cac6c5840 with Yocto cross compiling for ARM on x86_64, but was seeing QA errors. They don't recommend installing in /usr/local/. I pulled the latest ver and now missing binary operator before token "(" 133 | #if __HAVE_FLOAT16 && __GLIBC_USE (IEC_60559_TYPES_EXT). Any idea? | 22:23 |
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| gromero | hi | 22:58 |
| gromero | I'm getting a syntax error like: ERROR: syntax error, unexpected TOK_REG, expecting TOK_ID | 22:58 |
| gromero | but it do can synthesize the .v file without any error | 22:59 |
| gromero | https://pastebin.com/raw/yfGg15yH | 22:59 |
| gromero | any clue on what exactly the parser is requesting there? | 22:59 |
| daveshah | "bit" is a SystemVerilog keyword | 23:00 |
| gromero | oh! | 23:00 |
| gromero | daveshah: thanks a lot. indeed :) | 23:01 |
| gromero | so it means that for simulation ir's a SystemVerilog parser and for synthesis it's only the synthesizable subset of Verilog? | 23:03 |
| gromero | s/ir's/it's/ | 23:03 |
| daveshah | Yosys doesn't do significant simulation in the traditional sense, any sim it does do goes through the same elaboration/synth | 23:17 |
| daveshah | It supports a subset of SystemVerilog features. bit as an alias for reg is one of them. | 23:18 |
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| ZirconiumX | Well, cxxrtl makes it look a lot like Verilator | 23:30 |
| gromero | daveshah: hrm but if it do goes through the same elaboration/synth, why the problematic code I've pasted do really synthetizes fine? | 23:32 |
| daveshah | ZirconiumX: Yes that's why I said traditional sense - in the context of parsing | 23:32 |
| daveshah | gromero: but it doesn't you said there was an error | 23:33 |
| ZirconiumX | gromero: AIUI your code should parse fine without -sv | 23:35 |
| ZirconiumX | You're not using anything actually SV in there | 23:35 |
| daveshah | Indeed, the problem is nothing to do with simulation or synthesis but SystemVerilog vs Verilog | 23:36 |
| gromero | ZirconiumX: daveshah ah got it. thanks :) | 23:37 |
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