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| corecode | janrinze: why overpriced? somebody had to design it, pay for parts, keep them in stock, etc. | 07:29 |
|---|---|---|
| corecode | i just noticed that coming out of programming, my design thinks that there is a new SPI transaction happening, but it is just the programming signals still being active | 07:33 |
| corecode | i wonder how to deal with that | 07:33 |
| whitequark | add a reset | 07:34 |
| corecode | i have a reset | 07:34 |
| whitequark | not long enough? | 07:34 |
| corecode | hm, maybe my spi peripheral doesn't use the reset | 07:35 |
| corecode | i guess i'm just using CS as reset there | 07:35 |
| corecode | different clock domain, etc. | 07:35 |
| corecode | yea i guess that's it | 07:35 |
| corecode | thanks | 07:35 |
| whitequark | np :) | 07:35 |
| whitequark | glad to be your rubber ducky | 07:36 |
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| corecode | well no, the reset was a good point | 10:23 |
| corecode | how does that even work, two reset signals | 10:23 |
| whitequark | evidently it doesn't? | 10:32 |
| whitequark | or do you mean you want two resets and asking how to do it? | 10:32 |
| corecode | so my spi input circuit uses CS as active low reset | 10:32 |
| corecode | but that means that this circuit will be active even while the rest of the design is in reset | 10:33 |
| whitequark | is the SPI block clocked by SPI clock or system clock? | 10:35 |
| whitequark | (I assume that's an asynchronous reset) | 10:35 |
| corecode | yes it is clocked by SPI clock | 10:40 |
| corecode | ah interesting, i use rising CS as reset | 10:41 |
| whitequark | do you have CDC between the SPI block and the rest of the circuit? | 10:47 |
| corecode | yes i do | 11:03 |
| corecode | for whole bytes and associated signals | 11:03 |
| whitequark | hmmm | 11:04 |
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