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| ZirconiumX | daveshah: So, my current Quartus exploits have me writing to EDIF. Which is a pain to debug when trying to map "a problem in the EDIF" to "a problem in the Verilog netlist" | 17:30 |
|---|---|---|
| ZirconiumX | Any tips/advice? | 17:30 |
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| daveshah | Yosys EDIF is very specific to Vivado | 18:05 |
| daveshah | Does Quartus have EDIF output? I would start looking at what it generates | 18:06 |
| ZirconiumX | daveshah: Nope, only input. But it seems that it accepts Yosys' EDIF output just fine | 18:13 |
| daveshah | FYI, there have been bugs in the past where the EDIF is accepted but it turns out eg cell port vectors are reversed | 18:14 |
| ZirconiumX | At the moment I have a Quartus issue where it complains that a DFFEAS port cannot be connected | 18:15 |
| ZirconiumX | Which I'm pretty sure means that it doesn't exist in hardware for the CV | 18:15 |
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| cr1901_modern | ZirconiumX: Idk if you tried this already, but you describing the problem in ##openfpga yesterday made me think of using C-reduce or the program its based off of (delta): https://github.com/csmith-project/creduce/tree/master/delta | 19:33 |
| tpb | Title: creduce/delta at master · csmith-project/creduce · GitHub (at github.com) | 19:33 |
| ZirconiumX | cr1901_modern: I have not, I'll admit, but my time is more limited than most | 19:51 |
| ZirconiumX | So, having sorted out the DFFEAS bug from a stupidly obscure error message | 19:52 |
| ZirconiumX | I now have a new and unique error message | 19:53 |
| cr1901_modern | ZirconiumX: I would help, but I don't have Altera installed and I'm not in a position to do so right now :( | 19:54 |
| cr1901_modern | (if you _wanted_ help I mean) | 19:54 |
| ZirconiumX | I definitely won't object | 19:54 |
| ZirconiumX | cr1901_modern: The error message itself is not particularly difficult to diagnose | 19:59 |
| ZirconiumX | Error (274007): Net name "GND_NET" is used multiple times, but should be used only once | 20:19 |
| ZirconiumX | I can't tell if this is Quartus being picky or EDIF being picky | 20:19 |
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| janrinze | on the topic of up5k, how are the boards? I have the lattice breakout and the upduino v2. The latter is notoriously bad in respect to the oscilator frequency stability. | 21:49 |
| janrinze | Seems there is a v2.1 now but i'm not sure if it is any good. Also the IceBreaker is seriously overpriced, i.m.h.o. (77 euro's) | 21:50 |
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| tnt | heh, I use the icebreaker and it's always been very reliable. Surely not the cheapest, but it's one of the best designed one. | 23:15 |
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