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| ZirconiumX | Are parameter names in Verilog case-sensitive? I'm assuming so, but it doesn't hurt to check. | 11:33 |
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| ZipCPU | ZirconiumX: Yes. All identifiers in Verilog are case-sensitive | 12:15 |
| ZirconiumX | So what am I meant to do about Quartus primitives where the parameters are not case-sensitive? | 12:15 |
| ZipCPU | That said, if you dare to use lowercase letters in your parameter names, you'll be using what's known as "Heathen Verilog". :p | 12:15 |
| ZipCPU | You mean ... Quartus is broken? | 12:16 |
| ZirconiumX | Why does this surprise you? | 12:16 |
| ZipCPU | Sigh | 12:16 |
| ZipCPU | Yosys isn't broken ;) | 12:16 |
| ZipCPU | With some hardware, the MAX10 for example, you can go from Yosys to Quartus with an EDIF file | 12:17 |
| ZirconiumX | But yeah, altsyncram #(.OpErAtIoN_mOdE("dual_port"), ...) is accepted by Quartus | 12:17 |
| ZipCPU | ... or was it a VQM file? I documented it in the first article on the MAX1000 | 12:17 |
| ZirconiumX | VQM. | 12:17 |
| ZirconiumX | Or at least that's what I currently emit | 12:17 |
| ZipCPU | IIUC, the problem is that VHDL isn't case-sensitive | 12:18 |
| ZirconiumX | EDIF appears to have been dropped in recent-ish Quartus versions? Or at least squirreled away out of sight from documentation | 12:18 |
| ZipCPU | So it might be a cross-language issue .... ?? | 12:18 |
| ZirconiumX | Hurray. | 12:18 |
| ZirconiumX | /s | 12:18 |
| ZipCPU | /s ? | 12:19 |
| ZirconiumX | This is going to require some fun `attrmap` calls | 12:19 |
| ZirconiumX | /s means sarcasm. | 12:19 |
| ZipCPU | Ah | 12:19 |
| ZirconiumX | Maybe it's a bit of personal preference, but SCREAMING CAPS LOCK IS A BIT DIFFICULT FOR ME TO READ | 12:21 |
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| whitequark | ZipCPU: ZirconiumX: Yosys has `attrmap -tocase` for this specific issue | 18:10 |
| ZipCPU | ^ +1. Thanks! | 18:11 |
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| develonepi3 | hi all: I just cross-compiled icestorm & arachne-pnr on a Ubuntu 16.04 for a RPi, using the yocto sdk. See "https://github.com/develone/raspberrypi2_yocto-zeus/blob/master/docpi4/icestor-arachne-pnr-CC.pdf" & "https://github.com/develone/raspberrypi2_yocto-zeus/blob/master/docpi4/testing_cross_compile.txt". I tested creating a catzip.bin from catzip.blif & catzip.pcb. I tested the catzip.bin on my catboard, it worked okay. The next steps | 18:34 |
| develonepi3 | will be to cross compile yosys & nextpnr. | 18:34 |
| ZirconiumX | Yeah, you really shouldn't use arachne-pnr anymore. | 19:00 |
| develonepi3 | Zirconiumx I understand, this was just testing the cross compile sdk, which uses "make -e" to override the environment variables with sdk variables.. | 19:33 |
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| janrinze | Is SPRAM still not yet inferred by yosys for up5k? | 20:38 |
| daveshah | Afraid not, yosys still has no support for combined readwrite ports | 20:41 |
| janrinze | daveshah: that's a bummer.. Okay, so I will need to do it manually. | 20:41 |
| janrinze | Already wondered why i had the bootloader code in my old up5k stuff | 20:42 |
| janrinze | Is there a tool to setup spram similar to readmemh ? would be helpful. | 20:46 |
| daveshah | No, SPRAM is not initialisable | 20:46 |
| janrinze | okay, then it makes sense. | 20:49 |
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