Friday, 2019-12-06

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ZirconiumXSo, I've been adding asynchronous set for synth_intel_alm, and now Yosys is spewing "Warning: Complex async reset for dff '\Q'."14:10
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ZirconiumXhttps://gist.github.com/ZirconiumX/fcd6761a630b3688956a9a63a0b13ed814:12
tpbTitle: dff_sim.v ยท GitHub (at gist.github.com)14:12
daveshahYes, that's a standard warning for DFF with both set and clear14:18
daveshahThey are usually not implementable, although it seems Intel is an exception14:18
ZirconiumXhttps://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/hdl/prim/prim_file_dffeas.htm14:20
tpbTitle: DFFEAS Primitive (at www.intel.com)14:20
ZirconiumXThis is my reference here14:20
mwkintel and old xilinx14:20
mwkI have that issue on my TODO list for that reason14:20
mwkyosys will warn you, but will make the right-ish cell anyway, except14:21
mwk1) it ignores the priority of the reset/set on input and always assumes priority of reset over set (which is what most vendors pick anyway, I think)14:22
mwk2) it will emit dumb redundant logic on the set input14:22
ZirconiumX1) holds for Intel, judging by the truth table14:23
mwkso... ignore the warning, I'll fix it sooner or later14:23
ZirconiumXNoted14:25
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ZirconiumX...Would it be better to use asynchronous load over async reset/set?14:46
ZirconiumXSince now I have async reset/set, and async load/data14:50
ZirconiumXWhich is effectively a duplicate14:50
mwknot really a duplicate, reset/set is strictly better15:06
mwkif you try to implement async set/reset in terms of async load, it's too easy to end up in glitchland15:06
mwkalso, it may be a good idea to use both and save some logic15:08
mwk$_DLATCHSR_* maps cleanly to async load/data + async reset + async set15:08
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mwk(yosys doesn't emit them at this point, but that's *also* on my list)15:10
daveshahECP5 actually has async load too, but it's totally unused by the vendor tools (unless you create an ncl file)15:15
ZirconiumXOkay, fair15:16
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