Sunday, 2019-12-08

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ZirconiumXSo, for the $alu cell, what would be a cell that would change BI at runtime as opposed to it being constant?18:00
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ZirconiumXdaveshah, maybe?18:16
daveshahHypothetically an adder/subtractor18:16
daveshahI don't know if Yosys maps these yet (from add sub and mux)18:17
daveshahBut it's something I've wanted to look at at some point18:17
ZirconiumXI'm wondering if trying to specialise based on CI and/or BI is worth it or not18:17
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daveshahBI=1 is a common case (subtractor)18:19
daveshahFixed BI and CI is much more common than variable18:19
ZirconiumXI've been inspecting the output of Quartus and it's interesting (to me) that comparisons are not done with carry chains18:20
ZirconiumXWhich is actually probably cmp2lut18:20
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daveshahNot just cmp2lut, we should probably have a mode in Yosys not to convert any compare to soft logic18:44
mwktbh I think we shouldcompletely dump convering compares to sub19:20
mwkit's completely bonkers19:21
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daveshahAgreed19:57
daveshahIf nothing else because it prevents any serious downstream optimisation19:58
mwkwell it's also horribly inefficient20:16
mwkat least on xilinx20:16
mwkyou could reduce area 2× by using the carry chain in a better way for the variable inputs case (two pairs of input bits per LUT)20:17
mwkand at least 5× when one of the inputs is const20:17
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