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| ZirconiumX | So, `help memory_bram` talks about `enable X` which is the number of "enable bits". Are these clock enables? Byte enables? Read/Write enables? | 18:09 |
|---|---|---|
| daveshah | Latter two | 18:10 |
| daveshah | read/write enables | 18:10 |
| daveshah | `enable X` means X read/write enables for a port each enabling a "byte" of width W/X (W being the width of the port) | 18:11 |
| daveshah | as an example, a 32-bit port with 8-bit byte enables would have `enable 4 ...` | 18:11 |
| ZirconiumX | Right, okay | 18:11 |
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| ZirconiumX | If I do something like `input [31:0] A, B;`, how wide is B? 32 or 1? | 18:40 |
| ZirconiumX | Given this is Verilog, I figured I'd best ask before deciding | 18:41 |
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| rvense | or maybe they get sixteen bits each | 19:10 |
| ZirconiumX | God I hope not. | 19:14 |
| rvense | the nets "A", "," and "B" are each 10 2/3 bit | 19:17 |
| rvense | ... i think the real answer is 32. i've used it like that, at least, in verilog that does what i expect. | 19:18 |
| ZipCPU | No, no, no ... | 19:24 |
| ZipCPU | input [31:0] A, B; would declare two 32-bit inputs, A and B | 19:25 |
| ZipCPU | If you use: `default_nettype none (highly recommended) then this should read: input wire [31:0] A, B; | 19:25 |
| ZirconiumX | I'm writing Yosys techmap passes, and mapping primitives is not a very fun process | 19:26 |
| ZipCPU | Enjoy ;) | 19:36 |
| * ZirconiumX cries | 19:36 | |
| ZirconiumX | Because of the lack of documentation on what I'm trying to do, I'm resorting to essentially compiler-driven development | 19:37 |
| ZirconiumX | Except that with error messages such as "WYSIWYG RAM primitive has too many bits", I've kinda hit a brick wall here. | 19:38 |
| ZipCPU | Sigh. | 20:06 |
| ZipCPU | One of those things I've never tried to do is to write my own techmap passes | 20:06 |
| ZirconiumX | I mean, techmap *is* a useful thing. | 20:06 |
| ZipCPU | Others here on the channel have. Hopefully they'll be able to pipe up with a word (or two) of encouragement | 20:07 |
| ZipCPU | What sort of items are you trying to map? | 20:07 |
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| ZirconiumX | https://gist.github.com/ZirconiumX/6f3686329ddb10abd33218d1643eb5cd | 20:33 |
| tpb | Title: errors.txt ยท GitHub (at gist.github.com) | 20:33 |
| ZirconiumX | Block RAM and LUT RAM | 20:34 |
| ZirconiumX | Ironically, Quartus itself doesn't instantiate primitive RAM blocks directly but instead instantiates a megafunction to lower to the correct primitive | 20:34 |
| ZipCPU | Cyclone-V? | 20:35 |
| ZirconiumX | ZipCPU: ^ | 20:35 |
| ZirconiumX | Yep | 20:35 |
| ZipCPU | Yeah, I've done some work with Quartus tools myself | 20:35 |
| ZipCPU | Just not with my Cyclone_V and Yosys (yet) | 20:35 |
| ZipCPU | Does Yosys support defparam? I didn't think so ... | 20:35 |
| ZirconiumX | You're looking at basically the lone person for Yosys-on-Cyclone-V | 20:35 |
| ZirconiumX | write_verilog -defparam | 20:36 |
| ZipCPU | Ah, okay | 20:36 |
| ZirconiumX | I think Quartus supports new-style parameter definitions #(...) but since synth_intel uses this, I'm following them | 20:36 |
| ZipCPU | So ... is yosys doing the techmap only to have Quartus choke? Or is Yosys itself choking on the techmap? | 20:37 |
| ZirconiumX | Quartus is the one choking on this | 20:37 |
| ZirconiumX | I'm writing a techmap pass to produce this code | 20:37 |
| ZipCPU | Is this the "right" code for what you are trying to create? | 20:37 |
| ZirconiumX | Except I'm having issues with the Quartus primitives | 20:37 |
| ZirconiumX | I have no idea what the "right" code is, because Quartus primitives have no public documentation | 20:38 |
| ZipCPU | Why not instantiate the same underlying design in Quartus and see what it does with it? | 20:38 |
| ZirconiumX | synth_intel uses an altsyncram megafunction for this, but I have a distaste for the Altera IP library | 20:39 |
| * ZipCPU shares ZirconiumX's distaste | 20:40 | |
| ZirconiumX | I helped 'quark with adding Quartus support to nMigen | 20:41 |
| ZirconiumX | The IP library is horrendously inconsistent | 20:41 |
| ZipCPU | Yosys hasn't done the CV before, tho, right? | 20:41 |
| ZipCPU | (CV = Cyclone-V) | 20:42 |
| ZirconiumX | It does, kinda, but the previous "maintainer" - dh73 - used a Cyclone IVe, and the two families are fairly different | 20:42 |
| ZirconiumX | So I have a custom script flow for Cyclone V, which includes things like LUTRAM and BRAM mapping | 20:43 |
| ZirconiumX | synth_intel has no LUTRAM mapping, and I had to disable BRAM mapping for CV because it tries to instantiate a CIV BRAM cell on a CV | 20:45 |
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