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| tnt | Does yosys have an option to just error out when a latch is inferred ? | 12:44 |
|---|---|---|
| tnt | that's like 99.9% of the time an error in a fpga design ... | 12:44 |
| pepijndevos | tnt select -assert-none t:$latch maybe? | 12:45 |
| whitequark | there's read_verilog -nolatches | 12:46 |
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| whitequark | which would result in a 'x | 12:46 |
| tnt | Right, but that doesn't stop the build. I really just want it to crash. | 12:47 |
| tnt | pepijndevos: I'll give that a shot. | 12:47 |
| pepijndevos | When yosys tells me "Trying to prove $equiv for \gnt_1: failed.", does that mean it found an error, or just that it could not prove it? | 12:48 |
| pepijndevos | And... any hints on finding the cause for this? | 12:48 |
| pepijndevos | ERROR: Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically). | 13:00 |
| pepijndevos | I tried to whitebox and flatten the post-synthesis result | 13:00 |
| pepijndevos | It seems flatten doesn't even have an -autoproc option | 13:01 |
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| pepijndevos | I have no clue what is going on anymore. I think my simulation flip-flop models are subtly broken, but no clue what's going on | 13:23 |
| mwk | tnt: it's going to be called $dlatch, not $latch | 13:29 |
| mwk | and you need that assert after the proc pass, but before synthesis | 13:29 |
| mwk | so it's rather unwieldy | 13:29 |
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| whitequark | pepijndevos: I'm not sure if equiv works for latches, actually | 13:37 |
| whitequark | er | 13:37 |
| whitequark | wait, no, thread collision | 13:37 |
| pepijndevos | hehe | 13:37 |
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| janrinze | when building nextpnr without gui we don't need the huge chipdb binaries? | 22:50 |
| ZirconiumX | janrinze: You still do | 22:56 |
| ZirconiumX | Because the huge chipdb binaries contain all the routing information nextpnr needs | 22:56 |
| janrinze | hmm. strange. I just built it now but the database files are nowhere to be found. Perhaps different names now? | 23:08 |
| daveshah | That's because they are linked into the binary | 23:08 |
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