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| pepijndevos | For wide luts, can I recursively map to $lut, or should I hand code it all the way? | 10:16 |
|---|---|---|
| pepijndevos | ECP5 has it hardcoded up to 7, but Gowin has 8-wide luts, so it'll be even more insane. | 10:16 |
| daveshah | I would probably do it recursively | 10:17 |
| daveshah | I think back when I did ecp5 there was a problem with recursive techmapping that's now fixed | 10:17 |
| pepijndevos | cool, good to know | 10:17 |
| daveshah | However, I wouldn't bother with wide LUTs without abc9 | 10:17 |
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| pepijndevos | why (not)? | 10:18 |
| daveshah | The way Yosys calls it old ABC thinks a LUT4 and LUT8 have the same delay | 10:18 |
| daveshah | This causes it to use way too many big LUTs hurting area | 10:19 |
| pepijndevos | Hurting *area*? Or did you mean timing? Or both? | 10:20 |
| daveshah | Area | 10:21 |
| daveshah | Because abc thinks using large LUTs will be much better for delay (its primary objective as Yosys calls it) | 10:21 |
| daveshah | than it actually is because the muxes add delay | 10:21 |
| pepijndevos | Right... hmmm... will try it out a bit. | 10:22 |
| daveshah | It would actually be possible to fix this by passing a LUT library in abc the same way as abc9 | 10:23 |
| daveshah | Just no one has bothered | 10:24 |
| pepijndevos | Is there a nice way to make a N-wide LUT in verilog for testing? | 10:33 |
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| pepijndevos | Great, abc deleted my code. | 10:54 |
| ZirconiumX | pepijndevos: I think you could instantiate a $lut cell, and I believe they're of parametric width | 11:11 |
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| pepijndevos | right | 11:12 |
| ZirconiumX | daveshah: would abc9 still be superior to abc if you passed in a LUT library? | 11:13 |
| pepijndevos | It's just a classic "you have a typo in a portname, but rather than warn you I'll delete your code" | 11:13 |
| ZirconiumX | pepijndevos: `default_nettype none | 11:13 |
| pepijndevos | ?? | 11:13 |
| ZirconiumX | Assuming you're working in Verilog here, anyway | 11:14 |
| pepijndevos | Yea, VHDL yells at you for stuff like that | 11:14 |
| pepijndevos | (I think at least... it just yells at you a lot more than Verilog, which I like) | 11:15 |
| ZirconiumX | If you typo a parameter name, my understanding is that Verilog thinks you're declaring a new parameter that gets ignored | 11:15 |
| ZirconiumX | And the old parameter stays at 'bx | 11:15 |
| pepijndevos | ... which is *totally* what I want 99% of the time *facepalm* | 11:15 |
| ZirconiumX | The fix is to tell Verilog not to think you're declaring a new parameter by using `default_nettype none | 11:16 |
| ZirconiumX | As I understand it, anyway, daveshah or whitequark would know more about this than me | 11:16 |
| whitequark | `default_nettype none is correct | 11:19 |
| whitequark | you could also use read_verilog -noautowire | 11:19 |
| mwk | wait, is it? | 11:19 |
| mwk | for parameters? | 11:19 |
| pepijndevos | So you just put that at the top of your file? | 11:19 |
| ZirconiumX | Yep | 11:20 |
| mwk | pepijndevos: yes | 11:20 |
| mwk | every verilog file should have that line at the top | 11:20 |
| pepijndevos | brb, making yosys PR | 11:20 |
| whitequark | yes, Verilog also completely ignores unused parameters | 11:21 |
| whitequark | well | 11:21 |
| mwk | how helpful of it | 11:21 |
| whitequark | it doesn't quite ignore them | 11:22 |
| pepijndevos | echO "`default_nettype none" > hdr.v; find . -fname *.v -exec cat hdr.v | 11:22 |
| whitequark | it's more that any parameters you define when instantiating a module take preference over the parameters you define when defining it* | 11:22 |
| pepijndevos | (this is broken) | 11:22 |
| whitequark | * unless you use localparam, in which case the *other* one gets ignored, I think | 11:22 |
| whitequark | yep. | 11:22 |
| mwk | aaaaaaaaaaaaaaaaaa | 11:23 |
| whitequark | it also does some bizarre lazy evaluation thing | 11:24 |
| whitequark | A parameter declared in a named block, task, or function can only be directly redefined using a defparam | 11:24 |
| whitequark | statement. However, if the parameter value is dependent on a second parameter, then redefining the second | 11:24 |
| whitequark | parameter will update the value of the first parameter as well (see 12.2.3). | 11:24 |
| whitequark | I guess that makes sense? | 11:25 |
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| ZirconiumX | pepijndevos: So how long is it until the Gowin flow uses VHDL techmap files? :P | 11:28 |
| * pepijndevos thinks | 11:29 | |
| pepijndevos | When yosys comes with VHDL support on by default. | 11:30 |
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| ZirconiumX | So presumably when GHDL is rewritten in C? | 11:34 |
| mwk | what is GHDL written in? | 11:35 |
| ZirconiumX | Ada | 11:36 |
| mwk | ... | 11:36 |
| mwk | of course | 11:36 |
| pepijndevos | There are a few others that are fairly complete, in Rust, Java, and Python | 11:38 |
| pepijndevos | They are also just parsers, they don't do any synthesis and elaboration | 11:39 |
| pepijndevos | Can't claim to understand this fully, but even integrating the Rust parser in Yosys would be a monumental effort I think. | 11:39 |
| pepijndevos | Anyone know the correct vim fu for Yosys indentation? | 11:40 |
| ZirconiumX | I'm not even sure Yosys is all that consistent with indentation | 11:40 |
| ZirconiumX | pepijndevos: judging by the .editorconfig, probably :set ts=8 sts=8 noet | 11:42 |
| * pepijndevos install editorconfig vim plugin | 11:46 | |
| pepijndevos | This is a good idea | 11:46 |
| pepijndevos | Oh no... the formatting was fucked up in some ways, and now it is fucked up in other ways :(((( | 11:53 |
| pepijndevos | fml | 11:59 |
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| pepijndevos | I'm just going to cry now... | 12:02 |
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