| *** tpb has joined #yosys | 00:00 | |
| *** emeb has quit IRC | 00:01 | |
| *** hughhalf has joined #yosys | 01:17 | |
| *** rohitksingh has joined #yosys | 01:49 | |
| *** rohitksingh has quit IRC | 01:56 | |
| *** rohitksingh has joined #yosys | 01:59 | |
| *** PyroPeter has joined #yosys | 02:25 | |
| *** citypw has joined #yosys | 02:59 | |
| *** rohitksingh has quit IRC | 03:29 | |
| *** rohitksingh has joined #yosys | 03:30 | |
| *** indy has quit IRC | 03:31 | |
| *** citypw has quit IRC | 03:38 | |
| *** citypw has joined #yosys | 03:39 | |
| *** _whitelogger has quit IRC | 05:15 | |
| *** _whitelogger has joined #yosys | 05:17 | |
| *** Jybz has joined #yosys | 05:18 | |
| *** _whitelogger has quit IRC | 05:54 | |
| *** _whitelogger has joined #yosys | 05:56 | |
| *** jakobwenzel has joined #yosys | 06:10 | |
| *** emeb_mac has quit IRC | 06:40 | |
| *** tpb has joined #yosys | 07:41 | |
| *** rohitksingh has quit IRC | 07:58 | |
| *** rohitksingh has joined #yosys | 08:05 | |
| *** rohitksingh has quit IRC | 08:26 | |
| *** MrBismuth has quit IRC | 08:27 | |
| promach | I mean how do I interface synth output from yosys to nextpnr-ice40 ? | 09:09 |
|---|---|---|
| daveshah | `synth_ice40 -json out.json` | 09:10 |
| promach | daveshah : thanks. By the way, how to remove all ice40 DFF in the case of using ltp command ? | 09:20 |
| promach | I mean for synth_ice40 | 09:21 |
| promach | it is ltp t:$_DFF_P_ %n for synth | 09:21 |
| daveshah | ltp t:SB_DFF* %n | 09:21 |
| promach | daveshah: what about for synth_ice40 ? | 09:21 |
| promach | Thanks, let me try | 09:22 |
| promach | ERROR: failed to place cell '$abc$80826$auto$blifparse.cc:492:parse_blif$84024_LC' of type 'ICESTORM_LC' | 09:26 |
| promach | Placing design failed. | 09:26 |
| promach | daveshah : I had this place error in nextpnr | 09:26 |
| daveshah | Is your design over utilised? | 09:27 |
| promach | Number of wires: 6514 | 09:28 |
| promach | Number of wire bits: 14957 | 09:28 |
| promach | Number of public wires: 1168 | 09:28 |
| promach | Number of public wire bits: 9091 | 09:28 |
| promach | Number of memories: 0 | 09:28 |
| promach | Number of memory bits: 0 | 09:28 |
| promach | Number of processes: 0 | 09:28 |
| promach | Number of cells: 8769 | 09:28 |
| promach | SB_CARRY 400 | 09:28 |
| promach | SB_DFF 232 | 09:28 |
| promach | SB_DFFE 432 | 09:28 |
| promach | SB_DFFESR 1968 | 09:28 |
| promach | SB_DFFESS 40 | 09:28 |
| promach | SB_DFFSR 248 | 09:28 |
| promach | SB_LUT4 5449 | 09:28 |
| promach | I am trying to fit into tinyFPGA BX | 09:28 |
| promach | the previous error was for lattice 1k FPGA | 09:28 |
| promach | the error below is for tinyFPGA BX | 09:29 |
| promach | ERROR: failed to place cell 'data_input[21]$sb_io' of type 'SB_IO' | 09:29 |
| promach | Placing design failed. | 09:29 |
| promach | daveshah: | 09:29 |
| daveshah | Sounds like you have too many IO pins | 09:29 |
| promach | does this mean pins overuse | 09:29 |
| promach | ok | 09:29 |
| *** cr1901_modern has quit IRC | 10:37 | |
| *** pie_ has quit IRC | 10:38 | |
| *** cr1901_modern has joined #yosys | 10:43 | |
| *** GoldRin has joined #yosys | 10:48 | |
| *** chipb has quit IRC | 10:48 | |
| *** pie_ has joined #yosys | 11:00 | |
| *** GoldRin has quit IRC | 11:54 | |
| *** cr1901_modern has quit IRC | 12:18 | |
| *** somlo has quit IRC | 13:07 | |
| *** chipb has joined #yosys | 13:17 | |
| *** somlo has joined #yosys | 13:21 | |
| *** cr1901_modern has joined #yosys | 13:33 | |
| *** emeb has joined #yosys | 13:52 | |
| *** dys has joined #yosys | 15:05 | |
| *** cr1901_modern has quit IRC | 15:42 | |
| *** Jybz has quit IRC | 16:01 | |
| *** citypw has quit IRC | 16:32 | |
| *** indy has joined #yosys | 17:21 | |
| *** cr1901_modern has joined #yosys | 17:24 | |
| ZirconiumX | wq: Idea for bugpoint - a -grep-like argument for "interesting" crashes. For example, you might ask it to bugpoint an assert on a specific line, but dump anything which contains the phrase "ERROR: Assert" | 17:31 |
| janrinze | number of cells seems too much too.. | 17:37 |
| daveshah | That's cells from a Yosys point of view. Some carries LUTs and DFFs will pack together | 17:42 |
| *** Max-P has quit IRC | 17:48 | |
| *** Max-P has joined #yosys | 17:55 | |
| janrinze | daveshah: the ecp5 board you were working on, is that available somewhere? | 18:08 |
| daveshah | No, I'm afraid it isn't | 18:08 |
| janrinze | it's like the versa but has hdmi and such, right? | 18:09 |
| daveshah | It might be at some point in the future depending on how things work out | 18:09 |
| daveshah | Yes | 18:09 |
| daveshah | https://github.com/daveshah1/TrellisBoard | 18:09 |
| tpb | Title: GitHub - daveshah1/TrellisBoard: Ultimate ECP5 development board (at github.com) | 18:09 |
| janrinze | yes, that one | 18:09 |
| janrinze | the ulx3s has a different ecp5 chip | 18:09 |
| janrinze | perhaps i should look into designing a daughterboard for the eval board from lattice | 18:10 |
| *** rohitksingh has joined #yosys | 18:34 | |
| *** Jybz has joined #yosys | 18:35 | |
| *** pie_ has quit IRC | 18:41 | |
| *** rohitksingh has quit IRC | 18:43 | |
| *** rohitksingh has joined #yosys | 18:48 | |
| *** pie_ has joined #yosys | 19:03 | |
| *** rohitksingh has quit IRC | 19:31 | |
| janrinze | daveshah: is there a tool to modify the BRAM in a ecp5 design like with ice40? | 19:34 |
| daveshah | No, there isn't | 19:35 |
| daveshah | Exactly the same concept could be used though | 19:35 |
| *** rohitksingh has joined #yosys | 19:35 | |
| janrinze | ECP5 support is relatively new, isn't it? | 19:35 |
| janrinze | or has a lot smaller user base? | 19:36 |
| daveshah | About a year old | 19:36 |
| daveshah | Compared to 4 years for iCE40 | 19:36 |
| janrinze | makes sense | 19:36 |
| janrinze | i really like how nextpnr makes ecp5 like the big brother of ice40 now :-) | 19:37 |
| emily | hm, how old is arachne-pnr? ~4 years too? | 19:39 |
| daveshah | Yeah, icestorm came first and arachne-pnr shortly after | 19:40 |
| sorear | What did we use pre arachne? | 19:48 |
| janrinze | daveshah: does nextpnr-ecp5 latch the output to I/O pins or do i have to do that explicitly? | 19:48 |
| ZirconiumX | whitequark: Managed to trigger yet another assert in FlowMap: ERROR: Assert `!lut_gates[breaking_lut].empty()' failed in passes/techmap/flowmap.cc:1273 | 19:49 |
| daveshah | sorear: there was nothing, just tools to explore bitstreams | 19:49 |
| daveshah | janrinze: no, it doesn't pack output registers automatically yet | 19:49 |
| daveshah | If that's what you mean by latch? | 19:49 |
| daveshah | Currently the output registers aren't supported at all | 19:50 |
| janrinze | daveshah: Okay then I/O can have delay in respect to a global clock, right? | 19:51 |
| daveshah | Yes | 19:51 |
| daveshah | For now, a DDR primitive is the best bet | 19:52 |
| *** rohitksingh has quit IRC | 19:52 | |
| janrinze | I see. I am running a 1024x786 VGA output and it is decent. when using a dithered image it shows somewhat. | 19:53 |
| janrinze | at almost 67 Hz refresh | 19:53 |
| janrinze | could also be the pll of course. | 19:54 |
| *** rohitksingh has joined #yosys | 19:55 | |
| janrinze | daveshah: DSP 18x18 mult is not inferred yet, right? | 19:55 |
| daveshah | No, but it will be soon | 19:55 |
| janrinze | 'automagically' ? :-) | 19:55 |
| daveshah | https://github.com/YosysHQ/yosys/pull/1359 | 19:56 |
| tpb | Title: DSP inference for Xilinx (improved for ice40, initial support for ecp5) by eddiehung · Pull Request #1359 · YosysHQ/yosys · GitHub (at github.com) | 19:56 |
| daveshah | Yup, for all multiplies above a certain size | 19:56 |
| janrinze | I'll have a look at that. | 19:58 |
| daveshah | It's a pretty monstrous PR because it includes Xilinx and iCE40 stuff too | 19:59 |
| daveshah | The idea is about infrastructure for DSPs as much as anything else | 20:00 |
| janrinze | for up5k I didn't mind to use the primitives. it was a little confusing at first to get it right but it works very well. | 20:02 |
| daveshah | Yeah, when there are only 8 of them anyway instantiation isn't so bad | 20:03 |
| *** Jybz has quit IRC | 20:03 | |
| janrinze | Only needed one for this design. | 20:04 |
| janrinze | It does have one DSP MULT18x18 now. so it looks like it works. | 20:06 |
| ZirconiumX | After entirely too many attempts, I now have a "minimal" repro for the FlowMap assert bug | 20:10 |
| ZirconiumX | Well, *a* FlowMap assert bug | 20:10 |
| ZirconiumX | Given I turned up more in the process of finding this one | 20:10 |
| * ZirconiumX updates Yosys, and it works fine | 20:20 | |
| * ZirconiumX sighs | 20:20 | |
| janrinze | daveshah: true dual port ram might be necessary to manually infer? | 20:29 |
| daveshah | Yes, afraid so | 20:29 |
| tnt | it's not called infer if you do it manually :) | 20:29 |
| janrinze | i noticed how yosys was struggling :-) | 20:29 |
| ZirconiumX | Good news: bug still exists | 20:41 |
| ZirconiumX | Bad news: the test case I spent *hours* with bugpoint on doesn't trigger the bug in the current version | 20:41 |
| *** emeb_mac has joined #yosys | 20:49 | |
| somlo | oh, xc7dsp now has a PR, neat! | 20:57 |
| *** rohitksingh has quit IRC | 21:00 | |
| *** rohitksingh has joined #yosys | 21:34 | |
| *** rohitksingh has quit IRC | 22:32 | |
| *** emeb has quit IRC | 23:25 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!