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| ZirconiumX | Huh, this is interesting: the Cyclone 10 GX ALM strongly resembles the Cyclone V ALM, and the Cyclone 10 LP ALM strongly resembles the Cyclone IV ALM | 12:10 |
|---|---|---|
| ZirconiumX | This is useful information | 12:10 |
| daveshah | Cyclone 10 is just a rebranded Cyclone IV | 12:15 |
| daveshah | which is just a die shrink of the Cyclone III | 12:15 |
| daveshah | Not even sure if the JTAG IDs changed | 12:15 |
| ZirconiumX | The LP seems like it | 12:16 |
| ZirconiumX | But the ALM is different between the GX and LP | 12:16 |
| daveshah | Ah yes, meant LP | 12:16 |
| daveshah | GX may well just be a V though | 12:16 |
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| ZirconiumX | It does appear to be a V | 12:17 |
| daveshah | Intel are too lazy to update the JTAG IDs so it's usually pretty obvious | 12:17 |
| daveshah | From memory of playing with the Cyclone III, the Quartus programmer actually asks you which device you have | 12:18 |
| daveshah | Most other companies (Lattice certainly) put the IDCODE in efuse/otp so they can do binning after production testing | 12:18 |
| ZirconiumX | So, it seems the Intel range is architecturally split into IV/10LP/MAX10 and V/10GX | 12:19 |
| ZirconiumX | Which is useful from a coding standpoint | 12:20 |
| ZirconiumX | Since Project Chibi documents the MAX10 (not very well >.>), that information should translate to the other two | 12:20 |
| daveshah | Yup | 12:21 |
| daveshah | There will doubtless be some equivalences to Stratix/Arrias too | 12:22 |
| daveshah | No FPGA company has *that* many different arches... | 12:22 |
| daveshah | Chibi documents the MAX V iirc | 12:23 |
| ZirconiumX | Ah, yes | 12:23 |
| ZirconiumX | The MAX V seems to be related to the IV LE | 12:24 |
| ZirconiumX | But the flop is more advanced, it appears | 12:25 |
| ZirconiumX | The MAX V LE appears to be from a Cyclone I? | 12:32 |
| daveshah | Yes, I think rqou mentioned something like that at the time | 12:32 |
| ZirconiumX | This handbook refers to it as just "Cyclone", so yeah | 12:32 |
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