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| trmm | how much difference is expected between two bitstreams with similar verilog inputs? | 14:37 |
|---|---|---|
| trmm | For faster cycle times, is there anyway to ask nextpnr to only use limited parts of the chip (so that more of the bitstream is "empty")? | 14:37 |
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| trmm | more context: I added faster reprogramming support to tinyprog so that it doesn't erase sectors that it doesn't need to and it seems that many small changes in the verilog leave much of the bitstream identical so there is a definite speedup from the patch | 14:39 |
| trmm | otherwise erasing and flashing the entire chip is around 60 KB/s, so a full bitstream takes about 12 seconds | 14:41 |
| trmm | with the partial update it can be as fast as the time to read the bitstream, around 600 KB/s for an identical one | 14:41 |
| cr1901_modern | I need to update/play with tinyprog again | 15:19 |
| cr1901_modern | last I used it was late September to add micropython support | 15:19 |
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| ZirconiumX | daveshah: Where did the names for the cells come from? I've read through the docs and the ECP5 cells mostly match the docs, but is it just to match the docs? | 15:59 |
| daveshah | ZirconiumX: usually either to match the vendor primitives or be obvious that they don't match (any TRELLIS_ or ICESTORM_ primitives) | 16:01 |
| ZirconiumX | Ah, okay | 16:01 |
| daveshah | trmm: region constraints are a bit of a work in progress | 16:02 |
| daveshah | However, because of the ECP5 bitstream structure if a design uses a significant number of IO it is likely a large number of frames will change | 16:02 |
| daveshah | Because of routing through them changing | 16:02 |
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| corecode | i guess i can't use enum with yosys? | 17:07 |
| FL4SHK | corecode: SV support is incredibly weak | 18:19 |
| ZirconiumX | corecode: unless you pony up for Verific | 18:50 |
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| corecode | boo | 20:04 |
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| emeb_mac | boo who? | 21:30 |
| ZipCPU | Why are you crying? | 21:42 |
| ZirconiumX | I have absolutely no idea who the best person to ask for this is, but Quartus and Yosys have a disagreement on whether Verilog generate for loops requires blocks to have names | 21:43 |
| ZirconiumX | So who's right, for the sake of writing portable Verilog? | 21:43 |
| daveshah | I think, at least in plain Verilog, generate blocks have to be named to have wires/regs declared inside them but not otherwise | 21:44 |
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| ZirconiumX | Here's the snippet Yosys accepts but Quartus complains about: https://gist.github.com/ZirconiumX/7ead4ac0a06afccb3b181558e8a70ccb | 21:49 |
| tpb | Title: test.v ยท GitHub (at gist.github.com) | 21:49 |
| ZipCPU | ZirconiumX: Yosys issues no errors for the block names, so ... I put them in when something has to work with Quartus | 21:49 |
| ZirconiumX | Thus why I'm asking which is correct :P | 21:49 |
| daveshah | I think Yosys is correct according to the newer standards but not original Verilog | 21:50 |
| bwidawsk | quartus claims to support verilog 2001 and SV 2005 | 21:50 |
| bwidawsk | neither work for me without the name | 21:50 |
| daveshah | istr there are differences in support between paid and free quartus | 21:50 |
| daveshah | There was a twitter thread about this a while ago | 21:51 |
| bwidawsk | I am using paid | 21:51 |
| bwidawsk | fwiw | 21:51 |
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| ZirconiumX | What does Yosys' "public wires" stat mean? | 22:04 |
| ZirconiumX | I/O pins or something? | 22:05 |
| daveshah | Wires that weren't created or processed by Yosys (eg without a dollar prefix name) | 22:05 |
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