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| bwidawsk | I don't know the architecture well, but you could catch the signal when at a prompt, or let it through while a command is running | 03:44 |
|---|---|---|
| bwidawsk | I'm happy to dig into it if people think the RFC is a good idea | 03:45 |
| bwidawsk | tnt, daveshah, ZirconiumX: ^^ | 03:45 |
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| trmm | on the ulx3s schematic the FLASH_SCK line is connected to U3, which matches the LPF file. | 16:40 |
| trmm | however, nextpnr says: | 16:40 |
| trmm | ERROR: IO pin 'flash_clk$tr_io' constrained to pin 'U3', which does not exist for package 'CABGA381'. | 16:40 |
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| trmm | ah, I see there is an issue already open about it: https://nuget.pkg.github.com/SymbiFlow/prjtrellis/issues/75 | 16:43 |
| tpb | Title: database for ECP5 CABGA381 is missing pin U3 · Issue #75 · SymbiFlow/prjtrellis · GitHub (at nuget.pkg.github.com) | 16:43 |
| daveshah | For the flash clock you should use the USRMCLK primitive anyway | 16:43 |
| daveshah | I'm not even sure if Diamond allows you to use the clock as a normal IO or forces you to use the primitive too | 16:44 |
| trmm | ERROR: No wire found for port USRMCLKTS on destination cell usrmclk_inst. | 16:50 |
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| daveshah | Is your trellis and nextpnr up to date? | 16:50 |
| daveshah | This was fixed fairly recently | 16:51 |
| trmm | last pulled in April, so I'll do an update | 16:51 |
| daveshah | Just updating nextpnr should be fine | 16:51 |
| daveshah | Think I fixed the nextpnr side sometime in may | 16:52 |
| trmm | trellis was up to date since you just merged my most recent pr. I'm rebuilding nextpnr now | 16:53 |
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| trmm | Is generating the chipdb bba files supposed to consume all physical memory in the known universe? | 17:01 |
| tnt | trmm: no ... just a few G | 17:03 |
| daveshah | There was a patch by whitequark recently to serialise building them | 17:04 |
| trmm | finally made it past the 85k file without triggering the oom. make -j8 was a mistake in this case... | 17:05 |
| daveshah | This is exactly what that patch was supposed to fix | 17:06 |
| trmm | ok, that fixed the USRMCLKTS issue | 17:12 |
| pepijndevos_ | ZirconiumX, PCB has shipped! | 17:17 |
| ZirconiumX | pepijndevos_: and now in a month you'll find out you fucked up | 17:17 |
| ZirconiumX | Did you add a ground plane? | 17:17 |
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| pepijndevos_ | ZirconiumX, yes I did. It's all 2 layer through hole stuff, so there is a lot that can be fixed. | 17:48 |
| ZirconiumX | I still think you should learn manual routing | 17:52 |
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| pepijndevos_ | I've routed some fairly big 2 and 4 layer PCBs, and it's my least favourite part of electronic design. That moment where you're just staring hopelessly at a giant ratsnest... I'm sure it gets better with experience, I've seen some pretty amazing routing jobs. | 17:56 |
| daveshah | Personally I find routing quite relaxing | 17:58 |
| pepijndevos_ | But for this project the whole point of it is kinda the automation IMO. Ideally I'd just compile directly to PCB. I wonder if nextpnr could help here... | 17:58 |
| daveshah | No, nextpnr is designed for highly constrained applications (i.e. FPGAs). It would be no good for ASICs let alone PCBs | 17:59 |
| pepijndevos_ | I've explained pcb layout to people as connect the dots for grownups. | 18:00 |
| pepijndevos_ | So how does ASIC place and route work? | 18:00 |
| daveshah | Placement isn't that different, just with free choice of location rather than fixex | 18:01 |
| daveshah | *fixed | 18:01 |
| daveshah | Routing I don't know the details but presumably similar enough to a PCB | 18:02 |
| pepijndevos_ | But I assume for the amount of transistors in a modern chip there is a lot less manual work than typical PCB layout... or ASIC design is a special kind of hell I don't want to end up in. | 18:03 |
| daveshah | Yes, most general ASIC routing is automated afaik | 18:03 |
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| daveshah | But I suspect some of the standard cells are routed by hand | 18:04 |
| pepijndevos_ | Sure | 18:04 |
| daveshah | the routing between those cells wouldn't usually be by hand | 18:04 |
| pepijndevos_ | So is there any oss asic pnr yet? Or do you feed the yosys netlist into commercial tools? | 18:05 |
| daveshah | Yes, there is http://opencircuitdesign.com/qflow/ | 18:05 |
| tpb | Title: Qflow (at opencircuitdesign.com) | 18:06 |
| daveshah | I think there was a tapeout of picorv32 with it recently | 18:06 |
| pepijndevos_ | awesome | 18:06 |
| daveshah | https://content.riscv.org/wp-content/uploads/2019/06/11.45-Mohamed-Kassem-efabless-riscv.workshop.zurich.201906-Copy.pdf | 18:06 |
| pepijndevos_ | whoa | 18:08 |
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| trmm | Thanks for the help with the ecp5 USRMCLK issue. The tinyfpga bootloader now works on the ulx3s board, which is so much faster than the bitbang JTAG | 20:28 |
| cr1901_modern | oh nice! | 20:31 |
| trmm | (The FTDI used by ujprog has only 3 megabaud link and requires sending 16 bytes for every byte of the bitstream, so it is very slow) | 20:35 |
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| cr1901_modern | I'd like to see more direct USB connections to FPGAs even if it's limited to 1.1 | 20:37 |
| cr1901_modern | err Full Speed* | 20:38 |
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| trmm | the tinyfpga-ex has all of the USB-C pins connected. I wonder how well that will work in practice | 22:09 |
| trmm | (or if everyone will just use the USB 2 pins) | 22:09 |
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