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| promach | Could anyone comment on https://www.eevblog.com/forum/fpga/asynchronous-reset-mechanism-of-d-flip-flop-in-yosys/?all ? | 04:58 |
|---|---|---|
| tpb | Title: asynchronous reset mechanism of D flip-flop in yosys - Page 1 (at www.eevblog.com) | 04:58 |
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| gmc | howdy folks, i was wondering, how do the a << b operators synthesize with yosys? is that even something yosys does, or is that down to arachne-pnr? | 12:41 |
| daveshah | gmc: https://github.com/YosysHQ/yosys/blob/master/techlibs/common/techmap.v#L76-L118 | 12:42 |
| tpb | Title: yosys/techmap.v at master · YosysHQ/yosys · GitHub (at github.com) | 12:42 |
| daveshah | this defines how a shift operator maps to logic | 12:43 |
| daveshah | later passes in Yosys (e.g. abc) will then map this to LUTs | 12:43 |
| gmc | interesting, thanks.. | 12:46 |
| gmc | not sure how a for loop would translate into lut's yet though | 12:49 |
| daveshah | This effectively creates muxes using ?: | 12:50 |
| daveshah | Those muxes are then mapped to LUTs further downstream (usually in the abc pass) | 12:50 |
| gmc | i was thinking a case statement, but something along those lines is what i expected | 12:50 |
| gmc | (then again a case would probably become a mux too) | 12:51 |
| daveshah | Yes, nothing is mapped directly a LUT - it all goes through intermdiate logic like muxes and optimisation first | 12:51 |
| gmc | i'm a bit confused as to how 'buffer = {buffer, (2**i)'b0};' is valid verilog though, but i guess this verilog is somehow special or maybe it is legal in some recent iteration of the standards? | 13:25 |
| daveshah | It may not be legal - this file is pretty much Yosys-specific anyway | 13:30 |
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| ZirconiumX | You could probably make it legal through something like `buffer = {buffer, {2**i{1'b0}}}`, right? | 13:37 |
| ZirconiumX | (mostly testing my own knowledge of Verilog here) | 13:38 |
| daveshah | Yes, that looks more correct | 13:38 |
| gmc | i don't think so, i believe the number of repetitions needs to be a constant | 13:43 |
| daveshah | In this case `i` can be considered constant | 13:44 |
| gmc | sure enough, if i try that it gives a 'error: A reference to a wire or reg (`i') is not allowed in a constant expression.' | 13:44 |
| gmc | (or well, iverilog does anyway, should try that with yosys for good measure) | 13:45 |
| gmc | oh vsim also doesn't like it | 13:45 |
| ZirconiumX | i is not a wire or a reg :P | 13:48 |
| gmc | i know that.. you tell iverilog and modelsim that ;) | 13:48 |
| gmc | but indeed, yosys doesn't complain about it.. | 13:51 |
| gmc | i'd still like to be able to simulate my hdl before synthesizing though :) | 13:51 |
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| ZirconiumX | That's why we have separate models of cells for simulation | 14:01 |
| ZirconiumX | gmc: https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simlib.v#L374-L466 | 14:02 |
| tpb | Title: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at github.com) | 14:02 |
| gmc | oh, i did not know yosys did simulation as well! | 14:04 |
| ZirconiumX | It doesn't, really | 14:04 |
| ZirconiumX | But you can use this to simulate a synthesized design | 14:04 |
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| pepijndevos_ | So what does the sim command do then, if not simulate? | 14:25 |
| daveshah | It does simulation, but not in the same way as a traditional Verilog simulator | 14:27 |
| daveshah | Yosys doesn't process stimuli, the event model, delays, etc | 14:27 |
| daveshah | instead the sim command allows a simple clock to be specified | 14:27 |
| gmc | hmm some other thing i've been trying to figure out with yosys is why https://pastebin.com/v2xs7bcq gives an error 'Warning: Identifier `\myfoo.BAR' is implicitly declared at implicit.v:35.' and 'Warning: Wire top.\myfoo.BAR is used but has no driver.' | 14:33 |
| tpb | Title: [VeriLog] module foo #( parameter BAR = 3'b111 )( input [2:0] in, output [ - Pastebin.com (at pastebin.com) | 14:33 |
| gmc | iverilog and modelsim are happy about it, and I think the verilog standard allows it, but then again there's so many standards and i'm new to verilog anyways (used vhdl before) | 14:33 |
| ZirconiumX | gmc: BAR is a parameter, not a wire/reg | 14:33 |
| gmc | ok, but if i write 'top_in = 3'b111' it's fine.. once i instantiate a module, isn't the parameter like a constant? | 14:35 |
| ZirconiumX | It's a constant inside the module, I believe | 14:36 |
| gmc | 3'b111 is not a wire/reg either | 14:36 |
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| ZirconiumX | I'm pretty sure BAR is out of scope here | 14:37 |
| gmc | hmm i was under the impression that you could always access anything in verilog in the hierarchy by walking through the hieracrhy with dot-seperated paths | 14:37 |
| gmc | and iverilog and modelsim think this is fine again.. | 14:38 |
| * ZirconiumX digs out the specification | 14:38 | |
| gmc | which one? :) | 14:38 |
| ZirconiumX | IEEE 1364-2005 | 14:38 |
| gmc | i was looking at 1800-2009, but hadn't found it yet | 14:39 |
| ZirconiumX | Yosys' SystemVerilog support is a bit shaky | 14:39 |
| gmc | i used this to synthesize: yosys -p "read_verilog implicit.v; synth_ice40 -top top -blif top.blif" -q | 14:40 |
| gmc | not sure what the default is, 1364-2005? | 14:40 |
| tnt | https://github.com/YosysHQ/yosys/issues/647 | 14:40 |
| tpb | Title: Internal module wires are not accessible using dot notation · Issue #647 · YosysHQ/yosys · GitHub (at github.com) | 14:40 |
| ZirconiumX | 4.10 Parameters | 14:40 |
| ZirconiumX | Verilog HDL parameters do not belong to either the variable or the net group. Parameters are not variables; they are constants. | 14:41 |
| ZirconiumX | In other words, it's not a net | 14:41 |
| ZirconiumX | So if I read this spec correctly, Yosys is correct here and iverilog/modelsim are wrong | 14:41 |
| gmc | interesting (and a bit disappointing :) | 14:42 |
| ZirconiumX | Do you want to define a constant with a name? | 14:42 |
| gmc | yes, i guess i will need to `define instead of (ab)using parameters for this | 14:42 |
| ZirconiumX | Actually parameters are fine for this | 14:43 |
| ZirconiumX | But you want to use `localparam` here | 14:43 |
| gmc | i had that before, but then changed it to parameter because of this implicit definition thing | 14:43 |
| ZirconiumX | For example, in module top, add `localparam FOO = 3'b111;`, and then you can reference `FOO` in `top`. | 14:43 |
| daveshah | I believe hierarchical references are primarily a simulation feature | 14:43 |
| daveshah | They might be valid in synthesis in some of the newer SystemVerilog standards | 14:44 |
| gmc | ah yes, but I want to define the constant values in the module (in my actual design the module is in a different file and `included) | 14:44 |
| gmc | correction, i had localparam, but had to refactor to parameter to satisfy modelsim.. | 14:45 |
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| corecode | hm, i can't pass -p and -s at the same time? | 15:18 |
| ZirconiumX | corecode: yes you can | 15:30 |
| ZirconiumX | But -p executes after -s, I believe | 15:30 |
| corecode | doesn't look like, at least not for my version | 15:37 |
| ZirconiumX | Which version do you have? | 15:37 |
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| corecode | compiled some weeks agin | 19:51 |
| corecode | oh no, chip simulation works, bitstream doesn't work. it does run, but not how i expect it to run - only one out of 6 channels has output | 19:52 |
| corecode | (u4k) | 19:52 |
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| corecode | very derp. | 20:04 |
| corecode | mcu fail | 20:04 |
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| bwidawsk | so check_label stuff in the script pass serves as both a sync point as well as bookends for the steps in synthesis you wish to run, is that accurate? | 22:10 |
| daveshah | bwidawsk: primarily, it allows you to use -run label or -run from:to | 22:11 |
| bwidawsk | so from a state sense, you can never expect the previous block has run... | 22:12 |
| daveshah | For FPGA synthesis usually it's fair to say any end user would run all the parts | 22:13 |
| daveshah | Partial runs would only be for debugging | 22:13 |
| bwidawsk | daveshah› thanks | 22:13 |
| daveshah | But the only state in the script itself should be the options | 22:13 |
| daveshah | All other state should be in the RTLIL netlist | 22:13 |
| daveshah | It's fair to assume that a previous block has run at some point in time | 22:14 |
| daveshah | But the design might have been dumped to a file and loaded again, for example, maybe for debugging | 22:14 |
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