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| FL4SHK | what is the state of VHDL support in Yosys? | 15:45 |
|---|---|---|
| FL4SHK | "nonexistent" is my guess. | 15:45 |
| FL4SHK | looks like it requires verific | 15:49 |
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| corecode | FL4SHK: what are you up to? | 15:58 |
| FL4SHK | Evaluating my options. | 16:00 |
| FL4SHK | I'm pretty happy with VHDL itself... | 16:00 |
| FL4SHK | I just hate classical Verilog | 16:00 |
| FL4SHK | I really like SystemVerilog and VHDL. | 16:00 |
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| vup2 | FL4SHK: https://github.com/YosysHQ/yosys/wiki/VHDL-frontend-efforts | 16:32 |
| tpb | Title: VHDL frontend efforts · YosysHQ/yosys Wiki · GitHub (at github.com) | 16:32 |
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| cr1901_modern | ghdlsynth isn't feature complete, but has meaningful yosys support. The NVC simulator is feature complete but doesn't have meaningful yosys support; the idea would be to generate yosys RTLIL from NVC. | 16:51 |
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| FL4SHK | oh hey, cr1901_modern, do I know you? | 17:12 |
| FL4SHK | looks like you're in at least one other channel I'm in... | 17:12 |
| FL4SHK | vup2, cr1901_modern : any way to use the yosys formal verification with that? | 17:13 |
| daveshah | I don't think either of those frontends support assert or PSL | 17:19 |
| daveshah | So your properties would have to be in SV | 17:19 |
| FL4SHK | Okay. Is that a big deal? | 17:19 |
| FL4SHK | I'm honestly just trying to figure out my best option going forward at this point. | 17:20 |
| FL4SHK | I think I'd prefer to just stick to SystemVerilog. | 17:20 |
| FL4SHK | now... I'd like to improve the yosys read_verilog -sv interface support | 17:21 |
| FL4SHK | it just... doesn't seem to support passing a parameter into an interface | 17:21 |
| FL4SHK | this is such a glaring issue | 17:21 |
| FL4SHK | https://paste.ee/p/GiSFB | 17:21 |
| FL4SHK | even without the localparam being in package, it doesn't work. | 17:22 |
| FL4SHK | it also doesn't seem to think the parameters of an interface are constant? | 17:22 |
| FL4SHK | such that, in that "Adder" module, I couldn't access the parameters of the interface that was passed in | 17:23 |
| FL4SHK | "couldn't detect width of signal" | 17:28 |
| FL4SHK | or, "Failed to detect width for parameter" | 17:32 |
| FL4SHK | appears to be a bug in evaluation of parameters inside packages? | 17:34 |
| daveshah | Yes, that looks like a bug | 17:43 |
| daveshah | also seem to have it some kind of issue in the frontend debugging, -dump_ast2 which usually helps with this kind of stuff is hitting an assert fail | 17:43 |
| FL4SHK | I'm gonna try to fix thi | 17:44 |
| FL4SHK | s | 17:44 |
| daveshah | Cheers! | 17:46 |
| daveshah | that would be great | 17:47 |
| FL4SHK | ...it's in "type2str" | 17:50 |
| FL4SHK | apparently it's an AstNodeType with value 95 | 17:51 |
| FL4SHK | which is just... | 17:51 |
| FL4SHK | hmmmmm | 17:51 |
| FL4SHK | how do I do debug build? | 17:51 |
| FL4SHK | I believe I found the thing to do with the makefile. | 17:53 |
| FL4SHK | make ENABLE_DEBUG=1 looks like it | 17:53 |
| FL4SHK | I was afraid of digging into this yesterday... but now I think I'm going to give it a shot | 17:57 |
| FL4SHK | oh, you know what that ast assert bug appears to be? | 18:01 |
| FL4SHK | Looks like there was no update of the X macro in type2str | 18:01 |
| FL4SHK | ...could stand to have a list of things there tbh | 18:02 |
| daveshah | Yes, that makes sense | 18:20 |
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| FL4SHK | Okay, I think this is too tough for me | 18:37 |
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| davos | hey all. I'm not able to get yosys to infer an SB_SPI. I have to add a (* keep *) tag to the module instance, for it to be inferred, so something is not quite right. I'm using an iceup5k-sg48. Im not seeing any warnings from yosys, it seems to silently optimize away the block, but I could just not be reading the yosys output correctly. Any recommendations on how to debug the issue further? the sb_spi is being used as a slave, im not | 20:50 |
| davos | even connecting a miso line, just SCK, SS, and MOSI, along with the internal SB ports. | 20:50 |
| davos | Thanks | 20:51 |
| daveshah | davos: it will only be optimised away if none of its outputs (including the system bus outputs) are used | 21:04 |
| daveshah | Most likely because other logic is being optimised away | 21:04 |
| daveshah | Looking for the names of the wires connected to those ports in the Yosys log output might help to debug this | 21:06 |
| davos | ok, thanks, thats a good sanity check. Its probably due to how im crossing the clock domain, from spi to rest of the logic; still new at this. for instance SCKI is 6mghz and SBCLKI is 12 mghz | 21:11 |
| davos | actually, the SB_SPI should cross the clock domain for me... i think. i get what your saying, is there a way to have yosys optimize my logic LESS aggressively? | 21:19 |
| tnt | davos: post your code somewhere | 21:28 |
| davos | im gonna fight with it for another round first haha. Ill be back later with either a KO or a code post. daveshah's comment narrows it down pretty well | 21:35 |
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