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| promach | For https://gist.github.com/promach/cf3ae626a85badad6cd822d3107c86b7#file-spidergon_router-v-L343 , why am I having this error "[spidergon_proof] base: spidergon_router.v:343: Warning: Range [1:-1] select out of bounds on signal `\data_input': Setting 1 LSB bits to undef." ? | 09:25 |
|---|---|---|
| tpb | Title: Spidergon Networks On Chip ยท GitHub (at gist.github.com) | 09:25 |
| promach | If I change (FLIT_DATA_WIDTH-1) to 7 , I have different error | 09:31 |
| promach | it seems like the verilog code parser treats (FLIT_DATA_WIDTH-1) and 7 differently. Note that FLIT_DATA_WIDTH has a value of 8 | 09:31 |
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| promach | ZipCPU: have you experienced similar issue previously ? | 10:37 |
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| ZipCPU | promach: Yes, I have had similar issues, but the were all traced in the end to issues within my own code | 11:21 |
| ZipCPU | In your case, lines 7-9 are missing the keyword "parameter" as are 11-13 | 11:22 |
| promach | ZipCPU: no | 11:37 |
| promach | I have added parameter as you advised, but same error | 11:38 |
| promach | I think I know why now | 11:43 |
| promach | I have one other bug | 11:43 |
| promach | I just got past this particular error | 11:47 |
| ZipCPU | I usually catch errors like these using Verilator--even if I don't synthesize with Verilator | 11:59 |
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| promach | now, I really like verilator linting feature | 12:04 |
| promach | ZipCPU | 12:04 |
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| ZipCPU | Why, did you find your bug? | 12:12 |
| promach | ZipCPU: verilator linting provides some other insights into my coding | 12:15 |
| ZipCPU | ;) | 12:15 |
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| FL4SHK | Verilator is really high quality software | 14:16 |
| FL4SHK | I've honestly considered switching to it for when I just need a simulator. | 14:17 |
| FL4SHK | It's le fast | 14:20 |
| FL4SHK | I'm surprised that GHDL is a GCC front end.... | 14:21 |
| FL4SHK | Holy crap is that cool | 14:21 |
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