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| FL4SHK | It just... appears that they're not with the version I got from GitHub | 00:01 |
|---|---|---|
| FL4SHK | I get a lot of | 00:02 |
| FL4SHK | Warning: Identifier `\MyInterfaceInstance.mysig_out' is implicitly declared. | 00:02 |
| FL4SHK | things like this ^ | 00:02 |
| FL4SHK | and then it treats them as 1-bit things. | 00:03 |
| FL4SHK | oooh | 00:10 |
| FL4SHK | maybe I'm not running the right commands | 00:10 |
| FL4SHK | "failed to detect width for identifier" | 00:16 |
| FL4SHK | ooooh | 00:17 |
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| FL4SHK | it appears that I've found a bug | 00:33 |
| FL4SHK | https://paste.ee/p/GiSFB | 00:34 |
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| tnt | https://pastebin.com/iiVXGjtj | 12:55 |
| tpb | Title: [VeriLog] module top(BTN1, BTN2, BTN3, LED1, LED2); input BTN1, BTN2, BTN3; output L - Pastebin.com (at pastebin.com) | 12:55 |
| tnt | At line 6, is that valid in verilog ?!? | 12:55 |
| corecode | the initializer | 12:55 |
| corecode | ? | 12:55 |
| tnt | LED are the outputs | 12:56 |
| corecode | oh | 12:56 |
| corecode | then i don't understand what this is supposed to do | 12:57 |
| tnt | well my guess is the author just assumed it woudl 'connect' Sum[0] with LED1 'bidirectionally'. | 12:57 |
| tnt | like a physical wire ... | 12:58 |
| corecode | i see | 12:58 |
| tnt | but afaik ... it's wrong. | 12:58 |
| corecode | yes, that seems wrong | 12:58 |
| tnt | and yet yosys seems to accept it. | 12:59 |
| corecode | it looks like an initializer | 12:59 |
| daveshah | Yosys and LSE both seem to treat the = as bidirectional, Synplify and Verilator seem to treat it as unidirectional | 12:59 |
| corecode | oh interesting | 13:00 |
| corecode | i mean it doesn't make much sense to use an output as RHS? | 13:00 |
| tnt | I usually try to avoid it ... | 13:04 |
| tnt | I know in VHDL it's just forbidden. | 13:04 |
| corecode | the standard calls this net_decl_assignment | 13:05 |
| corecode | and it's in the 6.1 continuous assignment section | 13:06 |
| corecode | so that means there are two continuous assignments | 13:07 |
| tnt | yeah and the way I read it, it's clearly unidirectional. Value is _driven_ on the LHS whenever the RHS _changes_. | 13:09 |
| corecode | yes | 13:09 |
| corecode | can an output port be readable? | 13:10 |
| tnt | I'm trying to find that in the spec right now. | 13:11 |
| corecode | there are examples that imply that you can use output ports as RHS | 13:17 |
| corecode | 12.1.2 | 13:17 |
| corecode | i think it matters only for the module using the submodule | 13:18 |
| tnt | yup, afaict they are just normal wires so you can 'read' their values. | 13:19 |
| corecode | yea | 13:20 |
| corecode | so in this case, the problem is that there are two conflicting continuous assignments | 13:20 |
| corecode | and something bidirectional going on as well? | 13:20 |
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| FL4SHK | Did anyone happen to see what I mentioned last? | 16:43 |
| FL4SHK | I think I found a bug in yosys's SystemVerilog support. | 16:43 |
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| FL4SHK | well, I've made a fork. I'll see if I can fix it myself. | 18:08 |
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